公开(公告)号：US5487120A

公开(公告)日：1996-01-23

申请号：US193969

申请日：1994-02-09

申请人： Michael M. Choy ,  Paul E. Green, Jr. ,  William E. Hall ,  Frank J. Janniello ,  Jeff K. Kravitz ,  Karen Liu ,  Rajiv Ramaswami ,  Franklin F. Tong

发明人： Michael M. Choy ,  Paul E. Green, Jr. ,  William E. Hall ,  Frank J. Janniello ,  Jeff K. Kravitz ,  Karen Liu ,  Rajiv Ramaswami ,  Franklin F. Tong

IPC分类号： H04J14/00 ,  H04B10/155 ,  H04B10/24 ,  H04J14/02 ,  G02B6/00 ,  G02B6/36

CPC分类号： H04J14/02 ,  H04B10/506 ,  H04B10/572

摘要： A wavelength division multiplexer (WDM) unit (12) includes a plurality of Input/Output cards (IOCs 14). Each IOC is bidirectionally coupled to I/O specific media (fiber or copper) and to two coaxial cables. Also bidirectionally coupled to the coaxial cables are a plurality of Laser/Receiver Cards (LRC 20). The interface between the IOCs and the LRCs is an Emitter Coupled Logic (ECL) electrical interface that is conveyed over the coaxial cables. Each LRC is bidirectionally coupled by two single mode fibers to an optical multiplexer and demultiplexer, embodied within a grating (24). An input/output port of the grating is coupled to a fiber link (28) that enables bidirectional, full duplex data communications with a second WDM. Each WDM also includes a Diagnostic Processor Card (DPC 28) that receives status signals from the IOCs and LRCs, that forwards the status signals on to an external processor, and which generates control information for the IOCs and LRCs.

摘要翻译： 波分复用器（WDM）单元（12）包括多个输入/输出卡（IOC 14）。 每个IOC双向耦合到I / O特定介质（光纤或铜）和两根同轴电缆。 还双向耦合到同轴电缆的是多个激光/接收卡（LRC 20）。 IOC和LRC之间的接口是通过同轴电缆传送的发射极耦合逻辑（ECL）电接口。 每个LRC通过两个单模光纤双向耦合到光学多路复用器和解复用器中，体现在光栅（24）内。 光栅的输入/输出端口耦合到能够与第二WDM进行双向全双工数据通信的光纤链路（28）。 每个WDM还包括诊断处理器卡（DPC 28），其接收来自IOC和LRC的状态信号，将状态信号转发到外部处理器，并且产生IOC和LRC的控制信息。

公开(公告)号：US4685687A

公开(公告)日：1987-08-11

申请号：US773322

申请日：1985-09-06

申请人： William E. Hall ,  Edward D. Gailey ,  George J. Ovanin

发明人： William E. Hall ,  Edward D. Gailey ,  George J. Ovanin

IPC分类号： B23B31/14 ,  B23B31/16 ,  B23B31/175 ,  B23Q3/12 ,  B23B31/12

CPC分类号： B23Q3/12 ,  B23B31/14 ,  B23B31/16195 ,  B23B31/39 ,  Y10T279/19 ,  Y10T279/1961 ,  Y10T279/3406 ,  Y10T279/35

摘要： A workholder for a machine tool or the like having a power assembly and a work gripping assembly that are separable to permit use of a plurality of work gripping assemblies and associated work gripping jaws of a size and shape to accommodate different workpieces. Work gripping assemblies with jaws pre-qualified to different workpieces can be exchanged quickly and automatically, as by use of a robot, when different parts are to be machined, while a single power assembly remains connected to the machine tool.

摘要翻译： 一种具有动力组件和工件夹紧组件的机床等的工作夹具，其可分离以允许使用尺寸和形状的多个工件夹持组件和相关联的作业夹爪以适应不同的工件。 通过使用机器人，当要加工不同的零件时，同时单个动力组件保持连接到机床上，可以快速自动地更换具有预先通过不同工件的夹爪的工件夹紧组件。

公开(公告)号：US08850557B2

公开(公告)日：2014-09-30

申请号：US13408170

申请日：2012-02-29

申请人： Richard H. Boivie ,  William E. Hall ,  Guerney D. H. Hunt ,  Suzanne K. McIntosh ,  Mark F. Mergen ,  Marcel C. Rosu ,  David R. Safford ,  David C. Toll ,  Carl Lynn C. Karger

发明人： Richard H. Boivie ,  William E. Hall ,  Guerney D. H. Hunt ,  Paul A. Karger ,  Suzanne K. McIntosh ,  Mark F. Mergen ,  Marcel C. Rosu ,  David R. Safford ,  David C. Toll

IPC分类号： G06F12/14 ,  G06F21/31

CPC分类号： G06F21/31 ,  G06F21/54 ,  G06F21/6218 ,  G06F2221/2105

摘要： Disclosed are a processor and processing method that provide non-hierarchical computer security enhancements for context states. The processor can comprise a context control unit that uses context identifier tags associated with corresponding contexts to control access by the contexts to context information (i.e., context states) contained in the processor's non-stackable and/or stackable registers. For example, in response to an access request, the context control unit can grant a specific context access to a register only when that register is tagged with a specific context identifier tag. If the register is tagged with another context identifier tag, the contents of the specific register are saved in a context save area of memory and the previous context states of the specific context are restored to the specific register before access can be granted. The context control unit can also provide such computer security enhancements while still facilitating authorized cross-context and/or cross-level communications.

摘要翻译： 公开了一种为上下文状态提供非分层计算机安全增强的处理器和处理方法。 处理器可以包括上下文控制单元，其使用与相应上下文相关联的上下文标识符标签来控制上下文对包含在处理器的不可堆叠和/或可堆叠寄存器中的上下文信息（即上下文状态）的访问。 例如，响应于访问请求，上下文控制单元可以仅在该寄存器被标记有特定上下文标识符标签时才向该寄存器授予特定上下文访问。 如果寄存器用另一个上下文标识符标记，则将特定寄存器的内容保存在存储器的上下文保存区域中，并且特定上下文的先前上下文状态将被恢复到特定寄存器，然后才能授予访问权限。 上下文控制单元还可以提供这样的计算机安全增强，同时还促进授权的交叉上下文和/或跨级通信。

公开(公告)号：US08619979B2

公开(公告)日：2013-12-31

申请号：US12823278

申请日：2010-06-25

申请人： Joel T. Ficke ,  William E. Hall ,  Terence B. Hook ,  Michael A. Sperling ,  Larry Wissel

发明人： Joel T. Ficke ,  William E. Hall ,  Terence B. Hook ,  Michael A. Sperling ,  Larry Wissel

IPC分类号： G06F21/73 ,  H04L9/08

CPC分类号： G06F21/73 ,  H04L9/08 ,  H04L9/0866 ,  H04L9/3278

摘要： Electronic devices and methods are disclosed to provide and to test a physically unclonable function (PUF) based on relative threshold voltages of one or more pairs of transistors. In a particular embodiment, an electronic device is operable to generate a response to a challenge. The electronic device includes a plurality of transistors, with each of the plurality of transistors having a threshold voltage substantially equal to an intended threshold voltage. The electronic device includes a challenge input configured to receive the challenge. The challenge input includes one or more bits that are used to individually select each of a pair of transistors of the plurality of transistors. The electronic device also includes a comparator to receive an output voltage from each of the pair of transistors and to generate a response indicating which of the pair of transistors has the higher output voltage. The output voltage of each of the pair of transistors varies based on the threshold voltage of each of the pair of transistors.

摘要翻译： 公开了电子装置和方法，以基于一对或多对晶体管的相对阈值电压来提供和测试物理上不可克隆的功能（PUF）。 在特定实施例中，电子设备可操作以产生对挑战的响应。 电子设备包括多个晶体管，多个晶体管中的每一个具有基本上等于预期阈值电压的阈值电压。 电子设备包括被配置为接收挑战的挑战输入。 挑战输入包括用于单独选择多个晶体管中的一对晶体管中的每一个的一个或多个位。 该电子设备还包括一个比较器，用于接收来自该对晶体管中的每一个的输出电压，并产生一个响应，该响应指示该对晶体管中的哪一个具有较高的输出电压。 该对晶体管中的每一个晶体管的输出电压根据该晶体管对的阈值电压而变化。

公开(公告)号：US08135937B2

公开(公告)日：2012-03-13

申请号：US12272261

申请日：2008-11-17

申请人： William E. Hall ,  Guerney D. H. Hunt ,  Paul A. Karger ,  Mark F. Mergen ,  David R. Safford ,  David C. Toll

发明人： William E. Hall ,  Guerney D. H. Hunt ,  Paul A. Karger ,  Mark F. Mergen ,  David R. Safford ,  David C. Toll

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/46 ,  G06F9/26 ,  G06F9/34

CPC分类号： G06F12/1036

摘要： A mechanism is provided, in a data processing system, for accessing memory based on an effective address submitted by a process of a partition. The mechanism may translate the effective address into a virtual address using a segment look-aside buffer. The mechanism may further translate the virtual address into a partition real address using a page table. Moreover, the mechanism may translate the partition real address into a system real address using a logical partition real memory map for the partition. The system real address may then be used to access the memory.

摘要翻译： 在数据处理系统中提供了一种基于由分区的进程提交的有效地址来访问存储器的机制。 该机制可以使用段间隔缓冲区将有效地址转换为虚拟地址。 该机制可以使用页表进一步将虚拟地址转换成分区实际地址。 此外，该机制可以使用分区的逻辑分区实际存储器映射将分区实际地址转换为系统实际地址。 然后可以使用系统实际地址来访问存储器。

公开(公告)号：US20110317829A1

公开(公告)日：2011-12-29

申请号：US12823278

申请日：2010-06-25

申请人： Joel T. Ficke ,  William E. Hall ,  Terence B. Hook ,  Michael A. Sperling ,  Larry Wissel

发明人： Joel T. Ficke ,  William E. Hall ,  Terence B. Hook ,  Michael A. Sperling ,  Larry Wissel

IPC分类号： H04L9/20

CPC分类号： G06F21/73 ,  H04L9/08 ,  H04L9/0866 ,  H04L9/3278

摘要： Electronic devices and methods are disclosed to provide and to test a physically unclonable function (PUF) based on relative threshold voltages of one or more pairs of transistors. In a particular embodiment, an electronic device is operable to generate a response to a challenge. The electronic device includes a plurality of transistors, with each of the plurality of transistors having a threshold voltage substantially equal to an intended threshold voltage. The electronic device includes a challenge input configured to receive the challenge. The challenge input includes one or more bits that are used to individually select each of a pair of transistors of the plurality of transistors. The electronic device also includes a comparator to receive an output voltage from each of the pair of transistors and to generate a response indicating which of the pair of transistors has the higher output voltage. The output voltage of each of the pair of transistors varies based on the threshold voltage of each of the pair of transistors.

摘要翻译： 公开了电子装置和方法，以基于一对或多对晶体管的相对阈值电压来提供和测试物理上不可克隆的功能（PUF）。 在特定实施例中，电子设备可操作以产生对挑战的响应。 电子设备包括多个晶体管，多个晶体管中的每一个具有基本上等于预期阈值电压的阈值电压。 电子设备包括被配置为接收挑战的挑战输入。 挑战输入包括用于单独选择多个晶体管中的一对晶体管中的每一个的一个或多个位。 该电子设备还包括一个比较器，用于接收来自该对晶体管中的每一个的输出电压，并产生一个响应，该响应指示该对晶体管中的哪一个具有较高的输出电压。 该对晶体管中的每一个晶体管的输出电压根据该晶体管对的阈值电压而变化。

公开(公告)号：US20100088739A1

公开(公告)日：2010-04-08

申请号：US12245964

申请日：2008-10-06

申请人： William E. Hall ,  Guerney D. H. Hunt ,  Paul A. Karger ,  Mark F. Mergen ,  David R. Safford ,  David C Toll

发明人： William E. Hall ,  Guerney D. H. Hunt ,  Paul A. Karger ,  Mark F. Mergen ,  David R. Safford ,  David C Toll

IPC分类号： G06F12/14 ,  G06F21/00

CPC分类号： G06F12/1483 ,  G06F21/629 ,  G06F21/71

摘要： Hardware mechanisms are provided for performing hardware based access control of instructions to data. These hardware mechanisms associate an instruction access policy label with an instruction to be processed by a processor and associate an operand access policy label with data to be processed by the processor. The instruction access policy label is passed along with the instruction through one or more hardware functional units of the processor. The operand access policy label is passed along with the data through the one or more hardware functional units of the processor. One or more hardware implemented policy engines associated with the one or more hardware functional units of the processor are utilized to control access by the instruction to the data based on the instruction access policy label and the operand access policy label.

摘要翻译： 硬件机制被提供用于执行对数据的指令的基于硬件的访问控制。 这些硬件机制将指令访问策略标签与要由处理器处理的指令相关联，并将操作数访问策略标签与要由处理器处理的数据相关联。 指令访问策略标签与指令一起通过处理器的一个或多个硬件功能单元传递。 操作数访问策略标签与数据一起通过处理器的一个或多个硬件功能单元传递。 与处理器的一个或多个硬件功能单元相关联的一个或多个硬件实现的策略引擎被用于基于指令访问策略标签和操作数访问策略标签来控制对数据的指令的访问。

公开(公告)号：US20080288780A1

公开(公告)日：2008-11-20

申请号：US12142007

申请日：2008-06-19

申请人： BRUCE L. BEUKEMA ,  Robert A. Drehmel ,  William E. Hall ,  Jamie R. Kuesel ,  Gilad Pivonia ,  Robert A. Shearer

发明人： BRUCE L. BEUKEMA ,  Robert A. Drehmel ,  William E. Hall ,  Jamie R. Kuesel ,  Gilad Pivonia ,  Robert A. Shearer

IPC分类号： H04L9/00

CPC分类号： G06F21/72 ,  H04L9/06 ,  H04L63/123 ,  H04L2209/125

摘要： Methods and apparatus for reducing the impact of latency associated with decrypting encrypted data are provided. Rather than wait until an entire packet of encrypted data is validated (e.g., by checking for data transfer errors), the encrypted data may be pipelined to a decryption engine as it is received, thus allowing decryption to begin prior to validation. In some cases, the decryption engine may be notified of data transfer errors detected during the validation process, in order to prevent reporting false security violations.

摘要翻译： 提供了减少与解密加密数据相关的延迟的影响的方法和装置。 而不是等到整个加密数据包被验证（例如，通过检查数据传输错误），加密的数据可以在被接收时被流水线化到解密引擎，从而允许在验证之前开始解密。 在一些情况下，可以向解密引擎通知在验证过程期间检测到的数据传输错误，以防止报告错误的安全违规。

公开(公告)号：US20080184674A1

公开(公告)日：2008-08-07

申请号：US11937968

申请日：2007-11-09

申请人： William E. Hall ,  Thomas P. McQueeny

发明人： William E. Hall ,  Thomas P. McQueeny

IPC分类号： B65B5/06

CPC分类号： B65D77/0433 ,  B65D5/4204 ,  B65D5/503 ,  B65D5/505

摘要： A system and method for packaging consumer products that include a number of individual pieces is provided. A pulp insert tray that includes a number of form fitting receiving locations to receive the individual pieces of the set separates and protects the individual pieces from damage resulting from uncontained packaging. A retainer may be used in association with the insert tray to provide additional support of the individual pieces, and assist in the final assembly of the packaged set. The use of pulp as the insert tray material provides significant ecological benefit.

摘要翻译： 提供了一种用于包装消费品的系统和方法，包括多个单件。 包括多个形状配件接收位置以容纳该组件的单个件的纸浆插入盘分离并保护各个件免受由未包装的包装造成的损坏。 可以与插入托盘相关联地使用保持器，以提供对各个件的附加支撑，并且有助于封装组件的最终组装。 使用纸浆作为插入托盘材料提供了显着的生态效益。

公开(公告)号：US5003508A

公开(公告)日：1991-03-26

申请号：US338557

申请日：1989-04-07

申请人： William E. Hall

发明人： William E. Hall

IPC分类号： G06F13/40 ,  G06F15/173

CPC分类号： G06F13/4022 ,  G06F15/17381

摘要： An apparatus for providing data communication between concurrently operating random access memory and processing devices includes a set of interface nodes interconnected in series by bidirectional buses. Each node includes means for reading data at selected addresses within a random access memory and means for selectively transmitting that data outwardly to either one or both of the nearest neighbor nodes to which it is connected. Each node also includes means for receiving data from any nearest neighbor node to which it is connected, for writing that data into a selected address of random access memory, and for forwarding that data to another nearest neighbor node. Each node attaches a selected distance field to data it transmits to a nearest neighbor node, the distance field indicating the relative address of an intended destination node in terms of the number of nodes between the forwarding node and an intended destination. Each node is further adapted to receive and forward to nearest neighbor nodes messages generated by a processing device connected thereto and for controlling node operation according to said messages. Each node also attached an identification field to data transmitted to a nearest neighbor node indicating whether the data is a message, or a part of a data transfer between memory devices.

摘要翻译： 用于在同时操作的随机存取存储器和处理设备之间提供数据通信的装置包括通过双向总线串联互连的一组接口节点。 每个节点包括用于在随机存取存储器内的选定地址处读取数据的装置，以及用于选择性地将该数据向外发送到其所连接的最近邻节点中的一个或两者的装置。 每个节点还包括用于从与其连接的任何最近邻节点接收数据的装置，用于将该数据写入随机存取存储器的选定地址，并将该数据转发到另一个最近邻节点。 每个节点将所选择的距离字段附加到其发送到最近邻节点的数据，该距离字段以转发节点和预定目的地之间的节点数量表示预期目的地节点的相对地址。 每个节点还适于接收和转发到由连接到其上的处理设备生成的最近邻居节点消息，以及根据所述消息来控制节点操作。 每个节点还将识别字段附加到发送到最近邻节点的数据，指示数据是消息还是存储器件之间的数据传输的一部分。