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公开(公告)号：US10340903B2
公开(公告)日：2019-07-02
申请号：US15725905
申请日：2017-10-05
Inventor： Woojoo Lee , Jae-Jin Lee , Sukho Lee , Kyuseung Han , Sang Pil Kim , Young Hwan Bae
Abstract: Provided is a semiconductor device including a target circuit, a monitoring circuit, and a voltage controller. The target circuit includes a transistor. The monitoring circuit is configured to measure a temperature of the target circuit or measure a delay time between an input and an output of the target circuit. The voltage controller is configured to adjust a driving voltage for driving the target circuit or a back-bias voltage for adjusting a threshold voltage of the transistor by referring to at least one of the temperature and the delay time. As the temperature increases, the delay time decreases.
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公开(公告)号：US12267631B2
公开(公告)日：2025-04-01
申请号：US17399603
申请日：2021-08-11
Inventor： Sukho Lee , Sang Pil Kim , Young Hwan Bae , Jae-Jin Lee , Kyuseung Han , Tae Wook Kang , Sung Eun Kim , Hyuk Kim , Kyung Hwan Park , Hyung-Il Park , Kyung Jin Byun , Kwang Il Oh , In Gi Lim
IPC: H04N7/52 , H04N7/01 , H04N7/08 , H04N7/088 , H04N21/236 , H04N21/488 , H04N5/278
Abstract: Disclosed is a network-on-chip including a first data converter that receives first image data and second image data from at least one image sensor and encodes one image data among the first image data and the second image data, into first data, based on whether the first image data is identical to the second image data and a second data converter that receives non-image data from at least one non-image sensor and encodes the received non-image data into second data. The network-on-chip outputs the first data and the second data to transmit the first data and the second data to an external server at a burst length.
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公开(公告)号：US20240378411A1
公开(公告)日：2024-11-14
申请号：US18421055
申请日：2024-01-24
Inventor： Kwang Il Oh , Tae Wook Kang , Hyuk Kim , Jae-Jin Lee
IPC: G06N3/04
Abstract: Disclosed is a spike neural network circuit, which includes an axon generating a spike input, a synapse performing a weight calculation and generating a membrane signal based on the weight calculation, and a neuron accumulating the membrane signal to generate a spike output, and the neuron includes a firing unit that compares a potential of a membrane node where the membrane signal is accumulated with a reference potential and fires based on the comparison result, membrane capacitors connected to the membrane node, a switch controller that outputs switching signals based on the firing of the firing unit, switches that connects each of membrane capacitors to one of a power supply voltage and a ground voltage in response to the switching signals, and a spike output generator that generates the spike output based on the plurality of switching signals and the firing of the firing unit.
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14.发明授权公开(公告)号：US11923882B2
公开(公告)日：2024-03-05
申请号：US17212252
申请日：2021-03-25
Inventor： Tae Wook Kang , Sung Eun Kim , Hyung-Il Park , Jae-Jin Lee , Hyuk Kim , Kyung Hwan Park , Mi Jeong Park , Kyung Jin Byun , Kwang Il Oh , In Gi Lim
CPC classification number: H04B1/18 , H04B5/0031 , H04B13/005
Abstract: A hybrid communication device, an operation method thereof, and a communication system including the same are provided. The hybrid communication device includes a contact unit that includes an antenna for receiving a first communication signal and an electrode for receiving a second signal, a switch controller that includes a first switch and a second switch and controls the first switch and the second switch based on a change in capacitance of the electrode, and a signal processing unit that receives at least one of the first communication signal and the second communication signal from the contact unit via the first switch and processes the received signal. The first switch is connected to the contact unit, and the signal processing unit is connected to the first switch.
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公开(公告)号：US10438116B2
公开(公告)日：2019-10-08
申请号：US15804912
申请日：2017-11-06
Inventor： Kwang IL Oh , Sung Eun Kim , Seong Mo Park , Hyung-IL Park , Jae-Jin Lee , Joo Hyun Lee
Abstract: The present disclosure relates to a neuromorphic arithmetic device. The neuromorphic arithmetic device may include first and second synapse circuits, a charging/discharging circuit, a comparator, and a counter. The first synapse circuit may generate a first current by performing a first multiplication operation on a first PWM signal and a first weight, and the second synapse circuit may generate a second current by performing a second multiplication operation on a second PWM signal and a second weight. The charging/discharging circuit may store charges induced by the first current and the second current in a charging period, and may discharge the charges in a discharging period. The comparator may compare a voltage level of the charges discharged in the discharging period and a level of a reference voltage. The counter may count output pulses of an oscillator on the basis of a result of the comparison by the comparator.
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Patent Agency Ranking
公开(公告)号：US09836401B2
公开(公告)日：2017-12-05
申请号：US15222940
申请日：2016-07-28
Inventor： Jae-Jin Lee , Kyung Jin Byun , Nak Woong Eum
IPC: G06F12/08 , G06F12/084 , G06F9/30 , G06F12/0842 , G06F12/0875
CPC classification number: G06F12/084 , G06F9/3017 , G06F12/0842 , G06F12/0875 , G06F17/5022 , G06F2212/452 , G06F2212/62 , G06F2217/68
Abstract: Provided is a multi-core simulation method including allocating, to a working memory, a shared translation block cache commonly used for a plurality of core models, reading a first target instruction to be performed in a first core model, generating a first translation block corresponding to the first target instruction and provided with an instruction set used in a host processor, performing the first translation block in the first core model after the first translation block is stored in the shared translation block cache, reading a second target instruction to be performed in a second core model, searching the shared translation block cache for a translation block including same content as that of the second target instruction, and performing the first translation block in the second core model, when the first target instruction includes same content as that of the second target instruction.
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公开(公告)号：US20130205090A1
公开(公告)日：2013-08-08
申请号：US13757216
申请日：2013-02-01
Inventor： Jae-Jin Lee
IPC: G06F12/08
CPC classification number: G06F12/0811 , G06F15/17362
Abstract: Disclosed is a mufti-core processor having hierarchical communication architecture. The multi-core processor having hierarchical communication architecture is configured to include clusters in which cores are clustered; a lowest level memory shared among the cores included in the clusters; a middle level memory shared among the clusters; and a highest level memory shared by all the clusters. In accordance with an exemplary embodiment of the present invention, it is possible to improve the performance of the applications by reducing the communication overhead between respective core and supporting the data and functional parallelization.
Abstract translation: 公开了一种具有分层通信架构的多核处理器。 具有分层通信架构的多核处理器被配置为包括其中集群的集群; 在集群中包含的核心之间共享最低级别的内存; 在集群之间共享中间层的内存; 以及所有群集共享的最高级别的内存。 根据本发明的示例性实施例，通过减少各个核心之间的通信开销并支持数据和功能并行化，可以提高应用的性能。
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公开(公告)号：US12225464B2
公开(公告)日：2025-02-11
申请号：US17552766
申请日：2021-12-16
Inventor： Hyuk Kim , Hyung-Il Park , Tae Wook Kang , Sung Eun Kim , Mi Jeong Park , Kyung Jin Byun , Kwang Il Oh , Sukho Lee , Jae-Jin Lee , In Gi Lim , Kyuseung Han
Abstract: Disclosed is an operating method of a user communication device, which includes receiving a wakeup signal from a stationary communication device over a first human body communication channel, the wakeup signal having a frequency in a low frequency band, switching from a standby mode to a wakeup mode in response to the wakeup signal, and receiving a data signal from the stationary communication device over the first human body communication channel during the wakeup mode, and the first human body communication channel is provided by a body of a user of the user communication device.
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公开(公告)号：US11642026B2
公开(公告)日：2023-05-09
申请号：US16794718
申请日：2020-02-19
Inventor： Sung Eun Kim , Kwang Il Oh , Tae Wook Kang , Hyuk Kim , Mi Jeong Park , Hyung-Il Park , Kyung Jin Byun , Jae-Jin Lee , In Gi Lim
CPC classification number: A61B5/0028 , A61B5/117 , A61B5/683 , G06F3/03 , G06F3/044 , A61B2560/0209
Abstract: The human body sensing device includes a contact sensing unit that includes a sensing electrode and a signal electrode, an activation module that senses a contact with a body through the sensing electrode when the sensing electrode and the signal electrode contact the body and outputs a wake-up signal in response to the sensing of the contact, and a human body communication unit that provides a ground voltage to the signal electrode and outputs a data signal to the signal electrode when the wake-up signal from the activation module is received.
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公开(公告)号：US11607120B2
公开(公告)日：2023-03-21
申请号：US16378472
申请日：2019-04-08
Inventor： Kwang Il Oh , Hyung-Il Park , Tae Wook Kang , Sung Eun Kim , Mi Jeong Park , Jae-Jin Lee , In Gi Lim
Abstract: Provided are a capsule endoscopic receiving device, a capsule endoscope system including the same, and an operating method of the capsule endoscopic receiving device, the capsule endoscopic receiving device including an analog front end configured to receive a preamble from one receiving electrode pair from among a plurality of receiving electrodes, a valid signal detection circuit configured to compare a reference voltage with input data generated on a basis of a voltage level of the preamble, and a preamble processor configured to select a final electrode pair configured to receive the image data on a basis of a correlation value of the preamble and a comparison result of the input data and the reference voltage. According to the inventive concept, stability of receiving image data may be secured by selecting an optimal receiving electrode pair.
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