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11.发明申请METHOD, APPARATUS AND SYSTEM FOR REDUCED CHANNEL STARVATION IN A DMA ENGINE 有权DMA引擎中减少通道启动的方法，装置和系统公开(公告)号：US20110320645A1
公开(公告)日：2011-12-29
申请号：US12822046
申请日：2010-06-23
CPC分类号： G06F13/30
摘要： Techniques for generating information identifying a next direct memory access (DMA) task to be serviced. In an embodiment, arbitration logic provides a sequence of masking logic to determine, according to a hierarchy of rules, a next task to be serviced by a DMA engine. In certain embodiments, masking logic includes logic to mask information representing pending tasks to be serviced, the masking based on identification of a channel as being a suspended channel and/or a victim channel.
摘要翻译： 用于产生识别要维修的下一个直接存储器访问（DMA）任务的信息的技术。 在一个实施例中，仲裁逻辑提供了一系列屏蔽逻辑，以根据规则层级确定要由DMA引擎服务的下一个任务。 在某些实施例中，掩蔽逻辑包括屏蔽用于表示待服务的待处理任务的信息的逻辑，基于信道识别为暂停信道和/或受害信道的掩蔽。
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公开(公告)号：US20070239955A1
公开(公告)日：2007-10-11
申请号：US11394462
申请日：2006-03-30
申请人： Chee Teh , Suryaprasad Kareenahalli , Zohar Bogin
发明人： Chee Teh , Suryaprasad Kareenahalli , Zohar Bogin
IPC分类号： G06F13/28
CPC分类号： G06F13/1668 , G06F12/0215
摘要： Embodiments of a memory scoreboard are presented herein.
摘要翻译： 记忆记分板的实施例在本文中给出。
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公开(公告)号：US08930682B2
公开(公告)日：2015-01-06
申请号：US12969812
申请日：2010-12-16
IPC分类号： G06F9/30 , G06F9/345 , G06F9/38 , H04L12/861
CPC分类号： G06F9/345 , G06F9/30018 , G06F9/3009 , G06F9/3851 , H04L49/90
摘要： In one embodiment, the present invention is directed to a bit processor that includes an execution unit to, responsive to an instruction for access of data of a first bit width, access data of a second bit width, the second bit width having a different number of bits than the first bit width when some of the data accessed includes non-stream data. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明涉及一种位处理器，其包括执行单元，响应于访问第一位宽度的数据的指令，第二位宽度的访问数据，具有不同数量的第二位宽度 当某些访问的数据包括非流数据时，比第一位宽的位数。 描述和要求保护其他实施例。
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14.发明授权Direct memory access engine physical memory descriptors for multi-media demultiplexing operations 有权用于多媒体解复用操作的直接内存访问引擎物理内存描述符公开(公告)号：US08509254B2
公开(公告)日：2013-08-13
申请号：US12824300
申请日：2010-06-28
IPC分类号： G06F12/00
CPC分类号： G06F9/5027
摘要： The architecture and techniques described herein can improve system performance with respect to the following. Communication between two interdependent hardware engines, that are part of pipeline, such that the engines are synchronized to consume resources when the engines are done with the work. Reduction of the role of software/firmware from feeding each stage of the hardware pipeline when the previous stage of the pipeline has completed. Reduction in the memory allocation for software-initialized hardware descriptors to improve performance by reducing pipeline stalls due to software interaction.
摘要翻译： 本文描述的架构和技术可以改善系统性能。 两个相互依赖的硬件引擎之间的通信是管道的一部分，使得引擎在引擎完成工作时同步以消耗资源。 当管道的上一个阶段完成时，减少软件/固件从硬件管道的每个阶段的角色。 减少用于软件初始化的硬件描述符的内存分配，以通过减少由于软件交互而导致的流水线停顿来提高性能。
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公开(公告)号：US20120159128A1
公开(公告)日：2012-06-21
申请号：US12969812
申请日：2010-12-16
IPC分类号： G06F9/30
CPC分类号： G06F9/345 , G06F9/30018 , G06F9/3009 , G06F9/3851 , H04L49/90
摘要： In one embodiment, the present invention is directed to a bit processor that includes an execution unit to, responsive to an instruction for access of data of a first bit width, access data of a second bit width, the second bit width having a different number of bits than the first bit width when some of the data accessed includes non-stream data. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明涉及一种位处理器，其包括执行单元，响应于访问第一位宽度的数据的指令，第二位宽度的访问数据，具有不同数量的第二位宽度 当某些访问的数据包括非流数据时，比第一位宽的位数。 描述和要求保护其他实施例。
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公开(公告)号：US20110299680A1
公开(公告)日：2011-12-08
申请号：US12796502
申请日：2010-06-08
IPC分类号： H04L9/00
CPC分类号： H04N21/4405 , G06F21/10 , H04N21/4181 , H04N21/42623 , H04N21/4408
摘要： An apparatus for secured playback is presented. In one embodiment, the apparatus includes a controller that includes a key derivation module to manage authentication and key derivation. In one embodiment, the apparatus provides a video decryption key to a graphics engine if video data portions in a data stream are retrievable without having to decrypt the data stream. In one embodiment, the apparatus also includes a decryption module to decrypt a part of data in conjunction with an encryption key to generate video information and video data. The controller then writes an encrypted version of the video data to a video buffer of a graphics engine.
摘要翻译： 提出了一种用于安全播放的设备。 在一个实施例中，该装置包括控制器，该控制器包括用于管理认证和密钥推导的密钥导出模块。 在一个实施例中，如果可以检索数据流中的视频数据部分而不必对数据流进行解密，则该装置向图形引擎提供视频解密密钥。 在一个实施例中，该装置还包括解密模块，用于结合加密密钥对一部分数据进行解密以产生视频信息和视频数据。 然后，控制器将视频数据的加密版本写入图形引擎的视频缓冲器。
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17.发明申请公开(公告)号：US20100174841A1
公开(公告)日：2010-07-08
申请号：US12347973
申请日：2008-12-31
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Embodiments of apparatuses, methods, and systems for providing multiple virtual device controllers by redirecting an interrupt from a physical device controller are disclosed. In one embodiment, an apparatus includes a processor, a physical device controller, and virtualization logic. The virtualization logic is to receive a first interrupt from the physical device controller, and in response, send a second interrupt to the processor from one of a plurality of virtual device controllers.
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公开(公告)号：US07239254B1
公开(公告)日：2007-07-03
申请号：US11394510
申请日：2006-03-31
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03K5/135 , H03K5/15066
摘要： A programmable multi-cycle signaling scheme provides synchronous communications over relatively large distances. An input digital data stream is de-multiplexed onto multiple conductors. The digital data stream is recreated at the far end of the conductors.
摘要翻译： 可编程多周期信令方案提供了相对较大距离的同步通信。 输入数字数据流被解复用到多个导体上。 在导体的远端重建数字数据流。
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公开(公告)号：US08705729B2
公开(公告)日：2014-04-22
申请号：US12971210
申请日：2010-12-17
CPC分类号： H04L9/0822 , H04L9/3263 , H04L2209/60
摘要： In some embodiments an embedded processor is to participate in cryptographic key exchange with an audio software application, and a key exchange communication path is coupled between the audio software application and the embedded processor. Other embodiments are described and claimed.
摘要翻译： 在一些实施例中，嵌入式处理器将参与与音频软件应用的加密密钥交换，并且密钥交换通信路径耦合在音频软件应用和嵌入式处理器之间。 描述和要求保护其他实施例。
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公开(公告)号：US08560764B2
公开(公告)日：2013-10-15
申请号：US12643131
申请日：2009-12-21
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G11C16/10 , G11C16/32
摘要： A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed.
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