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公开(公告)号：US08521006B2
公开(公告)日：2013-08-27
申请号：US12775003
申请日：2010-05-06
IPC分类号： H04N5/94
CPC分类号： G11B27/3027 , G11B27/28
摘要： Encoded data decoding techniques. A data decoding agent determines a data segment size for a packet that includes a header and a data segment. The data decoding agent determines a segment end location based, at least in part, on the data segment size. The data decoding agent processes subblocks of data from the data segment. The data decoding agent compares a current location to the segment end location to determine if a current subblock of data from the data segments contains the segment end location. The data decoding agent triggers an exception handler if the current subblock contains the segment end location.
摘要翻译： 编码数据解码技术。 数据解码代理确定包括报头和数据段的分组的数据段大小。 数据解码代理至少部分地基于数据段大小来确定段结束位置。 数据解码代理处理来自数据段的数据的子块。 数据解码代理将当前位置与段结束位置进行比较，以确定来自数据段的当前数据子块是否包含段结束位置。 如果当前子块包含段结束位置，则数据解码代理触发异常处理程序。
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公开(公告)号：US09100693B2
公开(公告)日：2015-08-04
申请号：US12796502
申请日：2010-06-08
IPC分类号： H04L29/06 , H04N21/4405 , H04N21/426 , H04N21/4408 , G06F21/10
CPC分类号： H04N21/4405 , G06F21/10 , H04N21/4181 , H04N21/42623 , H04N21/4408
摘要： An apparatus for secured playback is presented. In one embodiment, the apparatus includes a controller that includes a key derivation module to manage authentication and key derivation. In one embodiment, the apparatus provides a video decryption key to a graphics engine if video data portions in a data stream are retrievable without having to decrypt the data stream. In one embodiment, the apparatus also includes a decryption module to decrypt a part of data in conjunction with an encryption key to generate video information and video data. The controller then writes an encrypted version of the video data to a video buffer of a graphics engine.
摘要翻译： 提出了一种用于安全播放的设备。 在一个实施例中，该装置包括控制器，其包括用于管理认证和密钥推导的密钥导出模块。 在一个实施例中，如果可以检索数据流中的视频数据部分而不必对数据流进行解密，则该装置向图形引擎提供视频解密密钥。 在一个实施例中，该装置还包括解密模块，用于结合加密密钥对一部分数据进行解密以产生视频信息和视频数据。 然后，控制器将视频数据的加密版本写入图形引擎的视频缓冲器。
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公开(公告)号：US08930682B2
公开(公告)日：2015-01-06
申请号：US12969812
申请日：2010-12-16
IPC分类号： G06F9/30 , G06F9/345 , G06F9/38 , H04L12/861
CPC分类号： G06F9/345 , G06F9/30018 , G06F9/3009 , G06F9/3851 , H04L49/90
摘要： In one embodiment, the present invention is directed to a bit processor that includes an execution unit to, responsive to an instruction for access of data of a first bit width, access data of a second bit width, the second bit width having a different number of bits than the first bit width when some of the data accessed includes non-stream data. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明涉及一种位处理器，其包括执行单元，响应于访问第一位宽度的数据的指令，第二位宽度的访问数据，具有不同数量的第二位宽度 当某些访问的数据包括非流数据时，比第一位宽的位数。 描述和要求保护其他实施例。
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4.发明授权Direct memory access engine physical memory descriptors for multi-media demultiplexing operations 有权用于多媒体解复用操作的直接内存访问引擎物理内存描述符公开(公告)号：US08509254B2
公开(公告)日：2013-08-13
申请号：US12824300
申请日：2010-06-28
IPC分类号： G06F12/00
CPC分类号： G06F9/5027
摘要： The architecture and techniques described herein can improve system performance with respect to the following. Communication between two interdependent hardware engines, that are part of pipeline, such that the engines are synchronized to consume resources when the engines are done with the work. Reduction of the role of software/firmware from feeding each stage of the hardware pipeline when the previous stage of the pipeline has completed. Reduction in the memory allocation for software-initialized hardware descriptors to improve performance by reducing pipeline stalls due to software interaction.
摘要翻译： 本文描述的架构和技术可以改善系统性能。 两个相互依赖的硬件引擎之间的通信是管道的一部分，使得引擎在引擎完成工作时同步以消耗资源。 当管道的上一个阶段完成时，减少软件/固件从硬件管道的每个阶段的角色。 减少用于软件初始化的硬件描述符的内存分配，以通过减少由于软件交互而导致的流水线停顿来提高性能。
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公开(公告)号：US20120159128A1
公开(公告)日：2012-06-21
申请号：US12969812
申请日：2010-12-16
IPC分类号： G06F9/30
CPC分类号： G06F9/345 , G06F9/30018 , G06F9/3009 , G06F9/3851 , H04L49/90
摘要： In one embodiment, the present invention is directed to a bit processor that includes an execution unit to, responsive to an instruction for access of data of a first bit width, access data of a second bit width, the second bit width having a different number of bits than the first bit width when some of the data accessed includes non-stream data. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明涉及一种位处理器，其包括执行单元，响应于访问第一位宽度的数据的指令，第二位宽度的访问数据，具有不同数量的第二位宽度 当某些访问的数据包括非流数据时，比第一位宽的位数。 描述和要求保护其他实施例。
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公开(公告)号：US20110299680A1
公开(公告)日：2011-12-08
申请号：US12796502
申请日：2010-06-08
IPC分类号： H04L9/00
CPC分类号： H04N21/4405 , G06F21/10 , H04N21/4181 , H04N21/42623 , H04N21/4408
摘要： An apparatus for secured playback is presented. In one embodiment, the apparatus includes a controller that includes a key derivation module to manage authentication and key derivation. In one embodiment, the apparatus provides a video decryption key to a graphics engine if video data portions in a data stream are retrievable without having to decrypt the data stream. In one embodiment, the apparatus also includes a decryption module to decrypt a part of data in conjunction with an encryption key to generate video information and video data. The controller then writes an encrypted version of the video data to a video buffer of a graphics engine.
摘要翻译： 提出了一种用于安全播放的设备。 在一个实施例中，该装置包括控制器，该控制器包括用于管理认证和密钥推导的密钥导出模块。 在一个实施例中，如果可以检索数据流中的视频数据部分而不必对数据流进行解密，则该装置向图形引擎提供视频解密密钥。 在一个实施例中，该装置还包括解密模块，用于结合加密密钥对一部分数据进行解密以产生视频信息和视频数据。 然后，控制器将视频数据的加密版本写入图形引擎的视频缓冲器。
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7.发明申请DIRECT MEMORY ACCESS ENGINE PHYSICAL MEMORY DESCRIPTORS FOR MULTI-MEDIA DEMULTIPLEXING OPERATIONS 有权直接存储器访问引擎用于多媒体解复用操作的物理存储器描述符公开(公告)号：US20110320777A1
公开(公告)日：2011-12-29
申请号：US12824300
申请日：2010-06-28
IPC分类号： G06F9/38
CPC分类号： G06F9/5027
摘要： The architecture and techniques described herein can improve system performance with respect to the following. Communication between two interdependent hardware engines, that are part of pipeline, such that the engines are synchronized to consume resources when the engines are done with the work. Reduction of the role of software/firmware from feeding each stage of the hardware pipeline when the previous stage of the pipeline has completed. Reduction in the memory allocation for software-initialized hardware descriptors to improve performance by reducing pipeline stalls due to software interaction.
摘要翻译： 本文描述的架构和技术可以改善系统性能。 两个相互依赖的硬件引擎之间的通信是管道的一部分，使得引擎在引擎完成工作时同步以消耗资源。 当管道的上一个阶段完成时，减少软件/固件从硬件管道的每个阶段的角色。 减少用于软件初始化的硬件描述符的内存分配，以通过减少由于软件交互而导致的流水线停顿来提高性能。
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公开(公告)号：US20180191494A1
公开(公告)日：2018-07-05
申请号：US15394324
申请日：2016-12-29
摘要： An embodiment of a graphics apparatus may include a graphics processor including a kernel executor, and a security engine communicatively coupled to the graphics processor. The security engine may be configured to create a kernel security key, encrypt an executable kernel for the kernel executor in accordance with the kernel security key, and share the kernel security key with the graphics processor.
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公开(公告)号：US20180308206A1
公开(公告)日：2018-10-25
申请号：US15698217
申请日：2017-09-07
申请人： Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L. Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
发明人： Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L. Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
CPC分类号： G06T1/20 , G06F3/0613 , G06F3/0659 , G06F3/0679 , G06F3/1438 , G06N3/0445 , G06N3/0454 , G06N3/063 , G06N3/08 , G06N3/084 , G06T1/60 , G09G5/001 , G09G5/363 , G09G2352/00 , G09G2360/06 , G09G2360/08 , G09G2360/121 , G09G2360/123 , G09G2370/08
摘要： An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.
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公开(公告)号：US20160189681A1
公开(公告)日：2016-06-30
申请号：US14582972
申请日：2014-12-24
申请人： Bryan R. White , Balaji Vembu , Murali Ramadoss , Altug Koker , Aditya Navale
发明人： Bryan R. White , Balaji Vembu , Murali Ramadoss , Altug Koker , Aditya Navale
CPC分类号： G09G5/18 , G06T1/20 , G09G5/026 , G09G5/14 , G09G5/363 , G09G2320/106 , G09G2340/02 , G09G2360/121 , G09G2360/18 , G09G2370/16
摘要： Described herein are technologies related to a ensuring that graphics commands and graphics context are offloading and scheduled for consumption as the commands and graphics context are sent from coherent to non-coherent memory/fabric in a “processor to processor” handoff or transaction.
摘要翻译： 这里描述的是与在“处理器到处理器”切换或事务中的命令和图形上下文从相干到非相干存储器/结构发送相关的确保图形命令和图形上下文被卸载并被调度用于消费的技术。
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