公开(公告)号：US4217640A

公开(公告)日：1980-08-12

申请号：US968522

申请日：1978-12-11

申请人： Marion G. Porter ,  Charles P. Ryan ,  William A. Shelly

发明人： Marion G. Porter ,  Charles P. Ryan ,  William A. Shelly

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0855

摘要： A data processing system comprises a data processing unit coupled to a cache unit which couples to a main store. The cache unit includes a cache store organized into a plurality of levels, each for storing a number of blocks of information in the form of data and instructions. Directories associated with the cache store contain addresses and level control information for indicating which blocks of information reside in the cache store. The cache unit further includes control apparatus and a transit block buffer comprising a number of sections each having a plurality of locations for storing read commands and transit block addresses associated therewith. A corresponding number of valid bit storage elements are included, each of which is set to a binary ONE state when a read command and the associated transit block address are loaded into a corresponding one of the buffer locations. Comparison circuits, coupled to the transit block buffer, compare the transit block address of each outstanding read command stored in the transit block buffer section with the address of each read command or write command received from the processing unit. When there is a conflict, the comparison circuits generate an output signal which conditions the control apparatus to hold or stop further processing of the command by the cache unit and the operation of the processing unit. Holding lasts until the valid bit storage element of the location storing the outstanding read command is reset to a binary ZERO indicating that execution of the read command is completed.

摘要翻译： 数据处理系统包括耦合到耦合到主存储器的高速缓存单元的数据处理单元。 高速缓存单元包括组织成多个级别的缓存存储器，每个级别用于以数据和指令的形式存储多个信息块。 与高速缓存存储相关联的目录包含用于指示哪些信息块驻留在高速缓存存储器中的地址和级别控制信息。 高速缓存单元还包括控制装置和传输块缓冲器，其包括多个部分，每个部分具有用于存储读取命令的多个位置和与其相关联的传输块地址。 包括相应数量的有效位存储元件，当将读取命令和相关联的传输块地址加载到相应的一个缓冲器位置时，其中的每一个被设置为二进制ONE状态。 耦合到传输块缓冲器的比较电路将存储在传输块缓冲器部分中的每个未完成读取命令的传输块地址与从处理单元接收的每个读取命令或写入命令的地址进行比较。 当存在冲突时，比较电路产生输出信号，该输出信号使控制装置保持或停止高速缓存单元对命令的进一步处理和处理单元的操作。 持续持续，直到存储未完成读取命令的位置的有效位存储元件被重置为指示执行读命令的二进制零。

公开(公告)号：US06754859B2

公开(公告)日：2004-06-22

申请号：US09752924

申请日：2001-01-03

申请人： Bruce E. Hayden ,  William A. Shelly

发明人： Bruce E. Hayden ,  William A. Shelly

IPC分类号： G11C2900

CPC分类号： G06F13/1663 ,  G06F12/0815

摘要： A plurality of processors in a data processing system share a common memory through which they communicate and share resources. When sharing resources, one processor needs to wait for another processor to modify a specified location in memory, such as unlocking a lock. Memory and bus traffic are minimized during this waiting by first reading and testing the memory location. Then, the memory location is not read and tested again until the local copy of the cache line containing that memory location is invalidated by another processor. This feature is utilized both for a Lock instruction and a Wait for Change instruction, both of which utilize a timer parameter for specifying a maximum number of cycles to wait for another processor to modify the specified location in memory.

摘要翻译： 数据处理系统中的多个处理器共享共同的存储器，通过它们进行通信和共享资源。 当共享资源时，一个处理器需要等待另一个处理器来修改存储器中的指定位置，例如解锁锁定。 在这个等待期间，通过读取和测试存储器位置，使存储器和总线流量最小化。 然后，直到含有该存储器位置的高速缓存行的本地副本被其他处理器无效之后，才会再次读取和测试存储器位置。 该功能既用于锁定指令和等待更改指令，两者都利用定时器参数来指定最大循环次数，以等待另一个处理器修改存储器中的指定位置。

公开(公告)号：US06351807B1

公开(公告)日：2002-02-26

申请号：US09160904

申请日：1998-09-25

申请人： Ron W. Yoder ,  Russell W. Guenthner ,  William A. Shelly ,  Eric Earl Conway ,  Boubaker Shaiek ,  Claude Rabel

发明人： Ron W. Yoder ,  Russell W. Guenthner ,  William A. Shelly ,  Eric Earl Conway ,  Boubaker Shaiek ,  Claude Rabel

IPC分类号： G06F935

CPC分类号： G06F9/30043 ,  G06F9/30141

摘要： A processor (40) in a data processing system simultaneously loads multiple registers (60) with a single value for fast domain switching. A domain switch instruction asserts a register block write signal (112) along with the register write signal (116) when block writing the single value to the set of registers (60). Register address lines (110, 111) are decoded in two sets: a first set of decoded address lines (110) specifying a block of registers; and the second set (111) specifying one register in the block of registers. When the register block write signal (112) is asserted during a register write, the second set of decoded address lines (111) are ignored, and all registers in the block of registers (60) selected by the first set of decoded address lines (110) are simultaneously loaded with a common value. Additional drive requirements are solved either by adding a buffer (226) to each register bit, or by disabling (228) the feedback path (215) in each register bit during block writes.

摘要翻译： 数据处理系统中的处理器（40）同时加载多个寄存器（60），其中单个值用于快速切换。 当将单个值写入寄存器集合（60）时，域切换指令与寄存器写入信号（116）一起断言寄存器块写入信号（112）。 寄存器地址线（110,111）被解码为两组：指定寄存器块的第一组解码地址线（110） 并且第二组（111）在寄存器块中指定一个寄存器。 当寄存器写入期间寄存器块写入信号（112）被置位时，第二组解码地址线（111）被忽略，并且由第一组解码地址线选择的寄存器块（60）中的所有寄存器 110）同时加载公共值。 额外的驱动器要求通过在每个寄存器位中添加缓冲器（226）或在块写入期间通过禁用（228）每个寄存器位中的反馈路径（215）来解决。

公开(公告)号：US5276862A

公开(公告)日：1994-01-04

申请号：US682801

申请日：1991-04-09

申请人： Lowell D. McCulley ,  Russell W. Guenthner ,  Clinton B. Eckard ,  Leonard Rabins ,  William A. Shelly ,  Ronald E. Lange ,  David S. Edwards

发明人： Lowell D. McCulley ,  Russell W. Guenthner ,  Clinton B. Eckard ,  Leonard Rabins ,  William A. Shelly ,  Ronald E. Lange ,  David S. Edwards

IPC分类号： G06F11/14 ,  G06F11/16 ,  G06F11/00

CPC分类号： G06F11/1441 ,  G06F11/1641 ,  G06F11/1637

摘要： In order to gather, store temporarily and deliver (if needed) central processor safestore information, a multiphase clock is employed to capture (one full clock cycle behind) the safestore information which typically includes all software visible registers in all (or selected) data manipulation chips of the CPU by routing the safestore information through temporary storage (under the influence of the multiphase clock) in a cache data array and into a special purpose XRAM module. Thus, upon the sensing of a fault, valid safestore information is available in the XRAM for analysis and, if appropriate, resumption of operation at a sequential point just previous to that at which the fault occurred.

摘要翻译： 为了收集，存储和交付（如果需要的话）中央处理器保险箱信息，采用多相时钟来捕获（一个完整的时钟周期）保存存储信息，这些信息通常包括所有（或选定的）数据操作中的所有软件可见寄存器 通过临时存储（在多相时钟的影响下）将缓存存储信息路由到高速缓存数据阵列中并进入特殊目的XRAM模块，从而使CPU的芯片。 因此，在检测到故障时，XRAM中有效的保险箱信息可用于分析，如果适用，在刚刚发生故障的连续点恢复运行。

公开(公告)号：US5263034A

公开(公告)日：1993-11-16

申请号：US594880

申请日：1990-10-09

申请人： Russell W. Guenthner ,  Clinton B. Eckard ,  Leonard Rabins ,  William A. Shelly ,  Ronald E. Lange ,  David S. Edwards ,  Bruce E. Flocken

发明人： Russell W. Guenthner ,  Clinton B. Eckard ,  Leonard Rabins ,  William A. Shelly ,  Ronald E. Lange ,  David S. Edwards ,  Bruce E. Flocken

IPC分类号： G06F11/16

CPC分类号： G06F11/1641

摘要： In order to provide efficient error detection in a central processor's Basic Processing Unit (BPU) including an AX (address and execution) module, a DN (decimal numeric) module and an FP (floating point) module, each module is provided redundantly in a master/slave pair, and the local result of data manipulation operations performed in each pair are compared for identity before the results are validated for subsequent use in the central processor.

摘要翻译： 为了在包括AX（地址和执行）模块，DN（十进制数字）模块和FP（浮点））模块的中央处理器的基本处理单元（BPU）中提供有效的错误检测，每个模块在 主/从对，并且将每个对中执行的数据操作操作的本地结果进行比较，以便在结果被验证以供后续在中央处理器中使用之前进行身份验证。

公开(公告)号：US4521851A

公开(公告)日：1985-06-04

申请号：US434122

申请日：1982-10-13

申请人： Leonard G. Trubisky ,  William A. Shelly

发明人： Leonard G. Trubisky ,  William A. Shelly

IPC分类号： G06F9/28 ,  G06F9/34 ,  G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3889 ,  G06F12/0848 ,  G06F9/34 ,  G06F9/3844 ,  G06F9/3863 ,  G06F9/3885

摘要： A central processor for a general-purpose digital data processing system. The processor has a pair of caches, an operand cache for operands and an instruction cache for instructions, as well as a plurality of execution units, where each execution unit executes a different set of instructions of the instruction repertoire of the central processor. An instruction fetch unit fetches instructions from the instruction cache and stores them in an instruction stack. The central pipeline unit which has five stages obtains instructions of a given program in program order from the instruction stack of the instruction fetch unit. In the first stage of the central pipeline unit, the instruction is decoded; in the second, the address preparation of an operand whose address is included in the instruction is initiated; in the third cycle, the address preparation is completed and the operand cache is accessed; in the fourth cycle, the operand is selected from the operand cache; and, in the fifth cycle, the instruction and operand are transmitted to the one of the plurality of execution units capable of executing the instruction. The results of the execution of each instruction by each execution unit are stored in a results stack associated therewith. A collector unit causes the results of the execution of the instructions of the program in execution to be stored in a master safe store register in program order, which is determined by the order of issuance of the instructions by the central pipeline unit. The collector also issues write commands to store results of the execution of instructions into the operand cache.

摘要翻译： 用于通用数字数据处理系统的中央处理器。 处理器具有一对高速缓存，用于操作数的操作数高速缓存和用于指令的指令高速缓存，以及多个执行单元，其中每个执行单元执行中央处理器的指令集的不同指令集。 指令提取单元从指令高速缓存中取出指令并将它们存储在指令栈中。 具有五个阶段的中央流水线单元从指令提取单元的指令堆栈获得给定程序的指令。 在中央流水线单元的第一阶段，指令被解码; 在第二个地址中，启动地址包含在指令中的操作数的地址准备; 在第三周期中，地址准备完成并且操作数缓存被访问; 在第四个周期中，从操作数缓存中选择操作数; 并且在第五周期中，指令和操作数被发送到能够执行指令的多个执行单元中的一个。 每个执行单元执行每个指令的结果被存储在与其相关联的结果堆栈中。 收集器单元使得执行中的程序的指令的执行结果以程序顺序存储在主安全存储寄存器中，该程序顺序由中央流水线单元发出指令的顺序确定。 收集器还发出写入命令以将执行指令的结果存储到操作数缓存中。

公开(公告)号：US4471432A

公开(公告)日：1984-09-11

申请号：US434196

申请日：1982-10-13

申请人： John E. Wilhite ,  William A. Shelly ,  Russell W. Guenthner ,  Leonard G. Trubisky ,  Joseph C. Circello

发明人： John E. Wilhite ,  William A. Shelly ,  Russell W. Guenthner ,  Leonard G. Trubisky ,  Joseph C. Circello

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3867

摘要： A method and a central execution pipeline unit for initiating the execution of instructions of a synchronous central processor unit (CPU) of a general-purpose digital data processing system. Instructions containing address information and an instruction field are obtained in program order from an instruction fetch unit of the CPU. In a first stage, requiring one clock period, the address information of an instruction is utilized to form the carrys and sums of an effective address and to initiate the formation of a virtual address. Concurrently, the instruction field is decoded to produce memory command signals and data alignment signals. In a second stage, the formation of the effective and virtual addresses initiated in the first stage is completed, and the word address portion of the virtual address is transmitted to the cache unit of the CPU. Also during the second stage, memory command signals are sent to the cache unit and the instruction field is converted to an execution code for one of a plurality of execution units, and the execution unit to execute the code is designated. In a third stage, the virtual address is converted to a physical address, or real page number, which is transmitted to the cache unit. The execution code is sent to the designated execution unit; however, if the execution unit is the central unit, the execution unit is the central unit, the execution code for that unit is converted into execution unit control signals. In the fourth stage, data alignment control signals are sent to a distributor of the central execution pipeline unit.

摘要翻译： 一种用于启动通用数字数据处理系统的同步中央处理器单元（CPU）的指令执行的方法和中央执行流水线单元。 从CPU的指令提取单元以程序顺序获取包含地址信息和指令字段的指令。 在需要一个时钟周期的第一阶段中，使用指令的地址信息来形成有效地址的进位和和并且启动虚拟地址的形成。 同时，指令字段被解码以产生存储器命令信号和数据对准信号。 在第二阶段中，完成在第一阶段中发起的有效和虚拟地址的形成，虚拟地址的字地址部分被发送到CPU的高速缓存单元。 此外，在第二阶段期间，存储器命令信号被发送到高速缓存单元，并且指令字段被转换为多个执行单元之一的执行代码，并且指定执行代码执行代码。 在第三阶段中，将虚拟地址转换为物理地址或实际页号，该地址被发送到高速缓存单元。 执行代码被发送到指定的执行单元; 然而，如果执行单元是中央单元，则执行单元是中央单元，该单元的执行代码被转换为执行单元控制信号。 在第四阶段，将数据对准控制信号发送到中央执行流水线单元的分配器。

公开(公告)号：US4006466A

公开(公告)日：1977-02-01

申请号：US562364

申请日：1975-03-26

申请人： Garvin Wesley Patterson ,  William A. Shelly ,  Jaime Calle ,  Earnest M. Monahan

发明人： Garvin Wesley Patterson ,  William A. Shelly ,  Jaime Calle ,  Earnest M. Monahan

IPC分类号： G06F13/12 ,  G06F9/46 ,  G06F9/48 ,  G06F13/26 ,  G06F1/00

CPC分类号： G06F9/4812 ,  G06F13/26 ,  G06F9/4818 ,  G06F9/4831

摘要： An input/output data processing system includes a plurality of active modules, a plurality of passive modules and at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. Each module connects to one of the ports by a plurality of different interfaces. The active modules include an input/output processing unit for processing interrupts and executing command sequences and a multiplexer unit for directly controlling transfers between the memory module and any one of the peripheral devices coupled to different ones of a plurality of ports of the multiplexer unit. Different ones of the modules of the system include the programmable interface used for transferring command information to the multiplexer unit and to the devices associated therewith for enabling a different type of control to proceed in parallel with input/output data transfer operations. Each multiplexer unit includes a plurality of storage registers which are operatively coupled to the programmable interface associated therewith for receiving control information therefrom designating the priority to be given by the unit to the processing of different types of interrupt signals received from devices associated therewith in addition to information designating which one of a set of processing routines to be used in servicing the interrupt.

摘要翻译： 输入/输出数据处理系统包括多个有源模块，多个无源模块和至少一个存储器模块和具有多个端口的系统接口单元，每个端口连接到不同的模块之一。 每个模块通过多个不同的接口连接到一个端口。 有源模块包括用于处理中断和执行命令序列的输入/输出处理单元和用于直接控制存储器模块与耦合到多路复用器单元的多个端口中的不同端口的任何外围设备之间的传输的多路复用器单元。 系统的不同模块包括用于将命令信息传送到多路复用器单元的可编程接口和与其相关联的设备，以使不同类型的控制与输入/输出数据传送操作并行进行。 每个多路复用器单元包括多个存储寄存器，其可操作地耦合到与其相关联的可编程接口，用于接收控制信息，从而指定由该单元给予的优先级，以处理从与其相关联的设备接收的不同类型的中断信号， 指定用于维护中断的一组处理例程中的哪一个的信息。

公开(公告)号：US06898738B2

公开(公告)日：2005-05-24

申请号：US09907302

申请日：2001-07-17

申请人： Charles P. Ryan ,  William A. Shelly ,  Stephen A. Schuerich

发明人： Charles P. Ryan ,  William A. Shelly ,  Stephen A. Schuerich

IPC分类号： G06F11/16 ,  G06F11/20 ,  G06F12/08 ,  G06F11/00

CPC分类号： G06F11/1666 ,  G06F11/167 ,  G06F11/20 ,  G06F12/0802

摘要： Cache memory, and thus computer system, reliability is increased by duplicating cache tag entries. Each cache tag has a primary entry and a duplicate entry. Then, when cache tags are associatively searched, both the primary and the duplicate entry are compared to the search value. At the same time, they are also parity checked and compared against each other. If a match is made on either the primary entry or the duplicate entry, and that entry does not have a parity error, a cache “hit” is indicated. All single bit cache tag parity errors are detected and compensated for. Almost all multiple bit cache tag parity errors are detected.

摘要翻译： 通过复制缓存标签条目，缓存内存，从而提高计算机系统的可靠性。 每个缓存标签都有一个主条目和一个重复条目。 然后，当关联搜索缓存标签时，将主条目和重复条目都与搜索值进行比较。 同时，他们也是平等检查和相互比较。 如果在主条目或重复条目上进行匹配，并且该条目没有奇偶校验错误，则指示缓存“命中”。 检测和补偿所有单位缓存标签奇偶校验错误。 检测到几乎所有多个位缓存标签奇偶校验错误。

公开(公告)号：US06530076B1

公开(公告)日：2003-03-04

申请号：US09472114

申请日：1999-12-23

申请人： Charles P. Ryan ,  Ron Yoder ,  William A. Shelly

发明人： Charles P. Ryan ,  Ron Yoder ,  William A. Shelly

IPC分类号： G06F944

CPC分类号： G06F11/3636 ,  G06F9/30185 ,  G06F11/28 ,  G06F11/3466

摘要： A processor (92) contains a Trace RAM (210) for tracing internal processor signals and operands. A first trace mode separately traces microcode instruction execution and cache controller execution. Selectable groups of signals are traced from both the cache controller (256) and the arithmetic (AX) processor (260). A second trace mode selectively traces full operand words that result from microcode instruction (242). Each microcode instruction word (242) has a trace enable bit (244) that when enabled causes the results of that microcode instruction (242) to be recorded in the Trace RAM (210).

摘要翻译： 处理器（92）包含用于跟踪内部处理器信号和操作数的跟踪RAM（210）。 第一个跟踪模式分别跟踪微代码指令执行和高速缓存控制器执行。 高速缓存控制器（256）和算术（AX）处理器（260）都可追踪可选组的信号。 第二跟踪模式选择性地跟踪由微代码指令（242）产生的全部操作数字。 每个微代码指令字（242）具有跟踪使能位（244），当使能时，使得该微代码指令（242）的结果被记录在跟踪RAM（210）中。