公开(公告)号：US5263034A

公开(公告)日：1993-11-16

申请号：US594880

申请日：1990-10-09

申请人： Russell W. Guenthner ,  Clinton B. Eckard ,  Leonard Rabins ,  William A. Shelly ,  Ronald E. Lange ,  David S. Edwards ,  Bruce E. Flocken

发明人： Russell W. Guenthner ,  Clinton B. Eckard ,  Leonard Rabins ,  William A. Shelly ,  Ronald E. Lange ,  David S. Edwards ,  Bruce E. Flocken

IPC分类号： G06F11/16

CPC分类号： G06F11/1641

摘要： In order to provide efficient error detection in a central processor's Basic Processing Unit (BPU) including an AX (address and execution) module, a DN (decimal numeric) module and an FP (floating point) module, each module is provided redundantly in a master/slave pair, and the local result of data manipulation operations performed in each pair are compared for identity before the results are validated for subsequent use in the central processor.

摘要翻译： 为了在包括AX（地址和执行）模块，DN（十进制数字）模块和FP（浮点））模块的中央处理器的基本处理单元（BPU）中提供有效的错误检测，每个模块在 主/从对，并且将每个对中执行的数据操作操作的本地结果进行比较，以便在结果被验证以供后续在中央处理器中使用之前进行身份验证。

公开(公告)号：US5276862A

公开(公告)日：1994-01-04

申请号：US682801

申请日：1991-04-09

申请人： Lowell D. McCulley ,  Russell W. Guenthner ,  Clinton B. Eckard ,  Leonard Rabins ,  William A. Shelly ,  Ronald E. Lange ,  David S. Edwards

发明人： Lowell D. McCulley ,  Russell W. Guenthner ,  Clinton B. Eckard ,  Leonard Rabins ,  William A. Shelly ,  Ronald E. Lange ,  David S. Edwards

IPC分类号： G06F11/14 ,  G06F11/16 ,  G06F11/00

CPC分类号： G06F11/1441 ,  G06F11/1641 ,  G06F11/1637

摘要： In order to gather, store temporarily and deliver (if needed) central processor safestore information, a multiphase clock is employed to capture (one full clock cycle behind) the safestore information which typically includes all software visible registers in all (or selected) data manipulation chips of the CPU by routing the safestore information through temporary storage (under the influence of the multiphase clock) in a cache data array and into a special purpose XRAM module. Thus, upon the sensing of a fault, valid safestore information is available in the XRAM for analysis and, if appropriate, resumption of operation at a sequential point just previous to that at which the fault occurred.

摘要翻译： 为了收集，存储和交付（如果需要的话）中央处理器保险箱信息，采用多相时钟来捕获（一个完整的时钟周期）保存存储信息，这些信息通常包括所有（或选定的）数据操作中的所有软件可见寄存器 通过临时存储（在多相时钟的影响下）将缓存存储信息路由到高速缓存数据阵列中并进入特殊目的XRAM模块，从而使CPU的芯片。 因此，在检测到故障时，XRAM中有效的保险箱信息可用于分析，如果适用，在刚刚发生故障的连续点恢复运行。

公开(公告)号：US5251321A

公开(公告)日：1993-10-05

申请号：US954437

申请日：1992-09-30

申请人： Donald C. Boothroyd ,  Clinton B. Eckard ,  Ronald E. Lange ,  William A. Shelly ,  Ronald W. Yoder

发明人： Donald C. Boothroyd ,  Clinton B. Eckard ,  Ronald E. Lange ,  William A. Shelly ,  Ronald W. Yoder

IPC分类号： G06F9/30 ,  H03M7/12 ,  G06F5/06

CPC分类号： G06F9/30025 ,  H03M7/12

摘要： Binary-Coded-Decimal to binary (DTB) and binary to Binary Coded Decimal (BTD) instructions are executed by an address and execution (AX) chip, a decimal numeric (DN) chip, and a cache. For a DTB instruction, the DN chip receives the operand to be converted from the cache, saves the sign, and stores it in a conversion register. When a bit is converted, a Ready-to-Send signal is sent on a COMFROM bus with a Ready-to-Receive Command on a COMTO bus causes the AX chip to accept the bit and the DN chip to generate the next bit until the resultant operand is produced. If the operand to be converted is negative, the DN chip inverts each remaining bit after the first "1" to obtain a two's-complement result. The result in either case is sent to the cache. For a BTD instruction, the AX chip receives the operand to be converted from the cache, send the sign bit to the DN chip and then the bits of the operand when the Ready-to-Send and Ready to Ready-to-Receive signals are produced. The resultant operand is sent to the conversion register. If the operand is negative, all bits are inverted, and a one is added to produce the resultant in two's complement notation.

摘要翻译： 二进制编码 - 十进制到二进制（DTB）和二进制到二进制编码十进制（BTD）指令由地址和执行（AX）芯片，十进制数字（DN）芯片和高速缓存执行。 对于DTB指令，DN芯片接收要从缓存转换的操作数，保存该符号，并将其存储在转换寄存器中。 当一个位被转换时，COMFROM总线上发送一个即时发送信号，COMTO总线上的就绪接收命令使AX芯片接受该位，并且DN芯片产生下一个位，直到 产生合成操作数。 如果要转换的操作数为负，则DN芯片在第一个“1”之后反转每个剩余的位，以获得二进制补码结果。 任一情况下的结果都将发送到缓存。 对于BTD指令，AX芯片接收要从高速缓存转换的操作数，将符号位发送到DN芯片，然后在即将发送和就绪准备就绪信号为零时，操作数的位 生产。 结果操作数被发送到转换寄存器。 如果操作数为负，则所有位都被反转，并且添加一个位以产生以二进制补码表示的结果。

公开(公告)号：US5644761A

公开(公告)日：1997-07-01

申请号：US893871

申请日：1992-06-05

申请人： Ronald W. Yoder ,  Ronald E. Lange ,  William A. Shelly ,  Russell W. Guenthner ,  Richard L. Demers

发明人： Ronald W. Yoder ,  Ronald E. Lange ,  William A. Shelly ,  Russell W. Guenthner ,  Richard L. Demers

IPC分类号： G06F9/26 ,  G06F9/22

CPC分类号： G06F9/267

摘要： In order to efficiently undertake the micro-steps required to execute an extended instruction in a central processing unit, a main sequence controller and a separate basic operations controller having its own sequencer and the ability to run semi-autonomously are provided. Normally, the main sequence controller determines the operation of the basic operations controller, but, in the case of execution of, for example, a multi-word instruction requiring extended basic operations, the basic operations controller temporarily takes control over the main controller until the extended basic operations have been completed. The result is a relatively simple sequencer that supports tight micro-coded functions where many of the sequence decisions can be predetermined.

摘要翻译： 为了有效地执行在中央处理单元中执行扩展指令所需的微步骤，提供了具有其自己的定序器的主序列控制器和单独的基本操作控制器以及半自主运行的能力。 通常，主序列控制器确定基本操作控制器的操作，但是在执行例如需要扩展基本操作的多字指令的情况下，基本操作控制器暂时控制主控制器，直到 扩展基本操作已经完成。 结果是相对简单的定序器，其支持紧密的微编码功能，其中许多顺序决定可以被预先确定。

公开(公告)号：US6052700A

公开(公告)日：2000-04-18

申请号：US156104

申请日：1998-09-17

申请人： Clinton B. Eckard ,  William A. Shelly

发明人： Clinton B. Eckard ,  William A. Shelly

IPC分类号： G06F1/12 ,  G06F1/14 ,  G06F12/08

CPC分类号： G06F11/26 ,  G06F11/2242 ,  G06F11/24 ,  G06F1/14 ,  G06F12/0833

摘要： Each processor (92) in a data processing system (80) caches a copy of the master calendar clock (97). The master calendar clock (97) and all of the cached calendar clocks (272) are periodically incremented utilizing a common clock (99). Whenever a processor (92) in the system (80) loads the master calendar clock (97) with a new value, that processor (92) broadcasts a cached calendar clock updated interrupt signal (276) to all of the processors in the system. In response to this interrupt (278), each processor (92) clears its cached calendar clock valid flag (274). Whenever a read calendar clock instruction is executed on a processor (92), the flag (274) is tested, and if set, its cached calendar clock (272) value is returned. Otherwise, the master calendar clock (97) value is retrieved, written to that processor's cached calendar clock (272), and returned. The cached calendar clock valid flag (274) is set to indicate a valid cached calendar clock (272).

摘要翻译： 数据处理系统（80）中的每个处理器（92）缓存主日历时钟（97）的副本。 使用公共时钟（99）来周期性地增加主日历时钟（97）和所有缓存的日历时钟（272）。 只要系统（80）中的处理器（92）以新值加载主日历时钟（97），该处理器（92）向系统中的所有处理器广播高速缓存的日历时钟更新的中断信号（276）。 响应于该中断（278），每个处理器（92）清除其缓存的日历时钟有效标志（274）。 每当在处理器（92）上执行读取日历时钟指令时，测试标志（274），并且如果被设置，则返回其高速缓存的日历时钟（272）值。 否则，检索主日历时钟（97）值，写入该处理器的缓存日历时钟（272）并返回。 高速缓存的日历时钟有效标志（274）被设置为指示有效的高速缓存日历时钟（272）。

公开(公告)号：US06351807B1

公开(公告)日：2002-02-26

申请号：US09160904

申请日：1998-09-25

申请人： Ron W. Yoder ,  Russell W. Guenthner ,  William A. Shelly ,  Eric Earl Conway ,  Boubaker Shaiek ,  Claude Rabel

发明人： Ron W. Yoder ,  Russell W. Guenthner ,  William A. Shelly ,  Eric Earl Conway ,  Boubaker Shaiek ,  Claude Rabel

IPC分类号： G06F935

CPC分类号： G06F9/30043 ,  G06F9/30141

摘要： A processor (40) in a data processing system simultaneously loads multiple registers (60) with a single value for fast domain switching. A domain switch instruction asserts a register block write signal (112) along with the register write signal (116) when block writing the single value to the set of registers (60). Register address lines (110, 111) are decoded in two sets: a first set of decoded address lines (110) specifying a block of registers; and the second set (111) specifying one register in the block of registers. When the register block write signal (112) is asserted during a register write, the second set of decoded address lines (111) are ignored, and all registers in the block of registers (60) selected by the first set of decoded address lines (110) are simultaneously loaded with a common value. Additional drive requirements are solved either by adding a buffer (226) to each register bit, or by disabling (228) the feedback path (215) in each register bit during block writes.

摘要翻译： 数据处理系统中的处理器（40）同时加载多个寄存器（60），其中单个值用于快速切换。 当将单个值写入寄存器集合（60）时，域切换指令与寄存器写入信号（116）一起断言寄存器块写入信号（112）。 寄存器地址线（110,111）被解码为两组：指定寄存器块的第一组解码地址线（110） 并且第二组（111）在寄存器块中指定一个寄存器。 当寄存器写入期间寄存器块写入信号（112）被置位时，第二组解码地址线（111）被忽略，并且由第一组解码地址线选择的寄存器块（60）中的所有寄存器 110）同时加载公共值。 额外的驱动器要求通过在每个寄存器位中添加缓冲器（226）或在块写入期间通过禁用（228）每个寄存器位中的反馈路径（215）来解决。

公开(公告)号：US4471432A

公开(公告)日：1984-09-11

申请号：US434196

申请日：1982-10-13

申请人： John E. Wilhite ,  William A. Shelly ,  Russell W. Guenthner ,  Leonard G. Trubisky ,  Joseph C. Circello

发明人： John E. Wilhite ,  William A. Shelly ,  Russell W. Guenthner ,  Leonard G. Trubisky ,  Joseph C. Circello

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3867

摘要： A method and a central execution pipeline unit for initiating the execution of instructions of a synchronous central processor unit (CPU) of a general-purpose digital data processing system. Instructions containing address information and an instruction field are obtained in program order from an instruction fetch unit of the CPU. In a first stage, requiring one clock period, the address information of an instruction is utilized to form the carrys and sums of an effective address and to initiate the formation of a virtual address. Concurrently, the instruction field is decoded to produce memory command signals and data alignment signals. In a second stage, the formation of the effective and virtual addresses initiated in the first stage is completed, and the word address portion of the virtual address is transmitted to the cache unit of the CPU. Also during the second stage, memory command signals are sent to the cache unit and the instruction field is converted to an execution code for one of a plurality of execution units, and the execution unit to execute the code is designated. In a third stage, the virtual address is converted to a physical address, or real page number, which is transmitted to the cache unit. The execution code is sent to the designated execution unit; however, if the execution unit is the central unit, the execution unit is the central unit, the execution code for that unit is converted into execution unit control signals. In the fourth stage, data alignment control signals are sent to a distributor of the central execution pipeline unit.

摘要翻译： 一种用于启动通用数字数据处理系统的同步中央处理器单元（CPU）的指令执行的方法和中央执行流水线单元。 从CPU的指令提取单元以程序顺序获取包含地址信息和指令字段的指令。 在需要一个时钟周期的第一阶段中，使用指令的地址信息来形成有效地址的进位和和并且启动虚拟地址的形成。 同时，指令字段被解码以产生存储器命令信号和数据对准信号。 在第二阶段中，完成在第一阶段中发起的有效和虚拟地址的形成，虚拟地址的字地址部分被发送到CPU的高速缓存单元。 此外，在第二阶段期间，存储器命令信号被发送到高速缓存单元，并且指令字段被转换为多个执行单元之一的执行代码，并且指定执行代码执行代码。 在第三阶段中，将虚拟地址转换为物理地址或实际页号，该地址被发送到高速缓存单元。 执行代码被发送到指定的执行单元; 然而，如果执行单元是中央单元，则执行单元是中央单元，该单元的执行代码被转换为执行单元控制信号。 在第四阶段，将数据对准控制信号发送到中央执行流水线单元的分配器。

公开(公告)号：US4594659A

公开(公告)日：1986-06-10

申请号：US434197

申请日：1982-10-13

申请人： Russell W. Guenthner ,  William A. Shelly ,  Gary R. Presley-Nelson ,  Kala J. Marietta ,  R. Morse Wade

发明人： Russell W. Guenthner ,  William A. Shelly ,  Gary R. Presley-Nelson ,  Kala J. Marietta ,  R. Morse Wade

IPC分类号： G06F9/38 ,  G06F9/28

CPC分类号： G06F9/3806 ,  G06F9/322 ,  G06F9/3889

摘要： Method and apparatus for prefetching instructions for a pipelined central processor unit for a general purpose digital data processing system. A table is maintained for purposes of predicting the target addresses of transfer and indirect instructions based on past history of the execution of those instructions. The prefetch mechanism forms instruction addresses and fetches instructions in parallel with the execution of previously fetched instructions by a central execution pipeline unit of the central processor unit. As instructions are prefetched, the transfer and indirect prediction (TIP) table is checked to determine the past history of those instructions. If no transfers or indirects are found, the prefetch proceeds sequentially. If transfer or indirect instructions are found, then the prefetch uses information in the TIP table to begin fetching the target instruction(s).The purpose of the prediction of target addresses is so that in the usual case instructions following a transfer can be executed at a rate of one instruction per pipeline cycle regardless of the pipeline depth or the frequency of transfers. Instructions are fetched two words at a time in order that the instruction fetch unit can stay ahead of the central execution pipeline. An instruction stack is provided for purposes of buffering double words of instructions fetched by the instruction fetch unit while waiting for execution by the central execution pipeline unit. The TIP table is updated based upon the actual execution of instructions by the central execution pipeline unit, and the correctness of the TIP table predictions is checked during execution of every instruction.

摘要翻译： 用于为通用数字数据处理系统的流水线中央处理器单元预取指令的方法和装置。 为了根据执行这些指令的过去历史来预测传送和间接指令的目标地址，维护表。 预取机制形成指令地址并且与由中央处理器单元的中央执行流水线单元执行先前获取的指令并行地获取指令。 当指令被预取时，检查传输和间接预测（TIP）表以确定那些指令的过去历史。 如果没有发现传输或间接，则预取将继续进行。 如果发现传输或间接指令，则预取使用TIP表中的信息开始获取目标指令。 目标地址的预测目的是为了在通常的情况下，无论流水线深度或传输频率如何，通常可以以每个流水线周期的一个指令的速率执行传送之后的指令。 指令一次取两个字，以便指令提取单元可以保持在中央执行管线之前。 提供指令堆栈用于缓冲​​由指令获取单元取得的指令的双字，同时等待中央执行流水线单元的执行。 TIP表基于中央执行流水线单元的指令的实际执行而被更新，并且在执行每个指令期间检查TIP表预测的正确性。

公开(公告)号：US5515529A

公开(公告)日：1996-05-07

申请号：US218538

申请日：1994-03-25

申请人： William A. Shelly ,  Ronald E. Lange ,  Donald C. Boothroyd

发明人： William A. Shelly ,  Ronald E. Lange ,  Donald C. Boothroyd

IPC分类号： G06F11/10 ,  G06F11/16 ,  G06F12/08 ,  G06F15/40

CPC分类号： G06F11/1633 ,  G06F11/10 ,  G06F12/0802

摘要： In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation operations, a first BPU transfers to cache storage only the even bits of a given data manipulation result, and a second BPU correspondingly transfers to cache storage only the odd bit information of the result. One BPU segregates the even bits of the result, adds parity information and sends the even bits and parity information to the cache unit. Similarly, the second BPU segregates the odd bits of the result, adds parity information and sends the odd bits and parity information to the cache unit. In the cache unit, the even and odd bit information are separately parity checked before storage into cache memory. If a parity error is observed in either set of information, an error signal is issued to institute appropriate remedial action.

摘要翻译： 为了验证在一个CPU中的数据操作结果，该CPU结合了重复的BPU以完整性，哪些BPU通常在单个VLSI电路芯片上实现，并且能够执行单精度和双精度数据操作操作，第一个BPU传输到缓存 仅存储给定数据操作结果的偶数位，并且第二BPU相应地将仅结果的奇数位信息传输到高速缓存存储器。 一个BPU分离结果的偶数位，添加奇偶校验信息，并将偶数位和奇偶校验信息发送到高速缓存单元。 类似地，第二BPU分离结果的奇数比特，添加奇偶校验信息，并将奇数比特和奇偶校验信息发送到高速缓存单元。 在高速缓存单元中，偶数和奇数比特信息在存储到高速缓冲存储器中之前被单独校验。 如果在任一组信息中观察到奇偶校验错误，则发出错误信号以进行适当的补救措施。

公开(公告)号：US5495579A

公开(公告)日：1996-02-27

申请号：US218532

申请日：1994-03-25

申请人： William A. Shelly ,  Ronald E. Lange ,  Donald C. Boothroyd

发明人： William A. Shelly ,  Ronald E. Lange ,  Donald C. Boothroyd

IPC分类号： G06F11/10 ,  G06F11/16 ,  G06F11/00

CPC分类号： G06F11/1654 ,  G06F11/10 ,  G06F11/1633

摘要： In order to validate data manipulation results in a CPU which incorporates duplicate basic processing units or integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation to obtain first and second data manipulation results, which should be identical, and a cache unit for receiving data manipulation results from both BPUs and for transferring specified information words simultaneously to both BPUs upon request. These operations are controlled by cache interface control signals identically generated in each BPU. In each BPU, the control signals are arranged into first and second groups which are nominally identical. The first control signal group is transmitted to the cache unit from one BPU while the second control group is transmitted to the cache unit from the other BPU. In each BPU, parity is generated for each control group separately. Parity for the group sent to the cache unit by each BPU is included with the control signal information for checking in the cache unit. Parity for the group not sent to the cache unit by each BPU is transmitted to the other BPU and checked against the locally generated parity for that group. In the event of a parity miscompare sensed in either BPU or a parity error sensed in the cache unit, an error signal is issued to institute appropriate remedial action.

摘要翻译： 为了验证包含重复基本处理单元或完整性的CPU中的数据处理结果，哪些BPU通常在单个VLSI电路芯片上实现，并且能够执行单精度和双精度数据操作以获得第一和第二数据 操作结果应该相同，以及用于从两个BPU接收数据操作结果并根据请求同时传送指定的信息字的缓存单元。 这些操作由在每个BPU中相同生成的高速缓存接口控制信号控制。 在每个BPU中，控制信号被布置成名义上相同的第一和第二组。 第一控制信号组从一个BPU发送到高速缓存单元，而第二控制组从另一个BPU发送到高速缓存单元。 在每个BPU中，分别为每个控制组生成奇偶校验。 用于由每个BPU发送到高速缓存单元的组的奇偶校验包括用于检查高速缓存单元的控制信号信息。 每个BPU未发送到高速缓存单元的组的奇偶校验被发送到另一个BPU，并针对该组的本地生成的奇偶校验进行检查。 在BPU中感测到的奇偶校验误差或在高速缓存单元中感测到的奇偶校验错误的情况下，发出错误信号以进行适当的补救动作。