公开(公告)号：US5629556A

公开(公告)日：1997-05-13

申请号：US486431

申请日：1995-06-07

申请人： F. Scott Johnson

发明人： F. Scott Johnson

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L27/082

CPC分类号： H01L29/66272 ,  H01L29/7322

摘要： A bipolar transistor (100) and a method for forming the same. A base-link diffusion source layer (118) is formed over a portion of the collector region (102). The base-link diffusion source layer (118) comprises a material that is capable of being used as a dopant source and is capable of being etched selectively with respect to silicon. A base electrode (114) is formed over at least one end portion of the base-link diffusion source layer (118) and the exposed portions of the base-link diffusion source layer (118) are removed. An extrinsic base region (110) is diffused from the base electrode (114) and a base link-up region (112) is diffused from the base-link diffusion source layer (118). Processing may then continue to form an intrinsic base region (108), emitter region (126), and emitter electrode (124).

公开(公告)号：US07572693B2

公开(公告)日：2009-08-11

申请号：US11462541

申请日：2006-08-04

申请人： F. Scott Johnson ,  Tad Grider ,  Benjamin P. McKee

发明人： F. Scott Johnson ,  Tad Grider ,  Benjamin P. McKee

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/04

CPC分类号： H01L21/28035 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted in to the exposed gate structure.

摘要翻译： 公开了用于半导体器件制造的方法，其中将掺杂剂选择性地注入到晶体管栅极结构中以抵消或补偿在随后的制造处理期间的掺杂剂耗尽。 图案化的注入掩模形成在半导体器件上，其暴露栅极结构的至少一部分并且覆盖器件的剩余上表面。 此后，将掺杂剂选择性地植入到暴露的栅极结构中。

公开(公告)号：US20080233695A1

公开(公告)日：2008-09-25

申请号：US11725417

申请日：2007-03-19

申请人： Shashank S. Ekbote ,  F. Scott Johnson

发明人： Shashank S. Ekbote ,  F. Scott Johnson

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807

摘要： A method of manufacturing a CMOS semiconductor comprising, forming shallow trench isolation regions in a workpiece, depositing a gate oxide layer on top of the workpiece, depositing a polysilicon layer on top of the gate oxide, performing VTN patterning, performing first series of adjusted implantations, performing post implantation cleaning, performing VTP patterning, performing a second series of adjusted implantations, performing the post implantation cleaning, performing a well implant damage anneal; patterning gate, etching gate, and performing back end of line processing.

摘要翻译： 一种制造CMOS半导体的方法，包括：在工件中形成浅沟槽隔离区域，在工件的顶部上沉积栅极氧化物层，在栅极氧化物的顶部上沉积多晶硅层，执行VT N N 图案化，执行第一系列调整的植入，执行植入后清洁，执行VT图案化，执行第二系列调整的植入，执行植入后清洁，执行井注入损伤退火; 图案化栅极，蚀刻栅极，以及执行线路处理的后端。

公开(公告)号：US06281530B1

公开(公告)日：2001-08-28

申请号：US09371647

申请日：1999-08-10

申请人： F. Scott Johnson

发明人： F. Scott Johnson

IPC分类号： H01L310336

CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L29/7304 ,  H01L29/735

摘要： A lateral PNP transistor (LPNP) (102) having the low resistance base buried N+ region (114) removed from below the emitter region (118). This leaves a high resistance n-well (116) below the emitter. The resistance from the center of the emitter region (118) to the N+ buried region (114) is greater than the resistance at the periphery of the emitter region (118) to the N+ buried region (114). Debiasing will occur in the center of the emitter region (118) where the parasitic base current is generated. Thus, the ratio of parasitic current to active collector current and peak beta will improve.

摘要翻译： 具有从发射极区域（118）下方去除的低电阻基极掩埋N +区域（114）的横向PNP晶体管（LPNP）（102）。 这使得在发射极下方留下高电阻n阱（116）。 从发射极区域（118）的中心到N +掩埋区域（114）的电阻大于在发射极区域（118）周围到N +掩埋区域（114）的电阻。 在发生寄生基极电流的发射极区域（118）的中心发生偏移。 因此，寄生电流与主动集电极电流和峰值β的比值将会提高。

公开(公告)号：US06248650B1

公开(公告)日：2001-06-19

申请号：US09215765

申请日：1998-12-18

申请人： F. Scott Johnson

发明人： F. Scott Johnson

IPC分类号： H01L2138

CPC分类号： H01L29/66272

摘要： A bipolar transistor includes a collector region, an intrinsic base region within the collector region, an extrinsic base region within the collector region. and a base link-up region within the collector region between the intrinsic base region and the extrinsic base region. An emitter region is positioned within the intrinsic base region. A base electrode overlays and is in electrical communication with a portion of the extrinsic base region and the base link-up region, and a doped inter-polysilicon dielectric layer overlays a portion of the base electrode. A capping layer is positioned above the inter-polysilicon dielectric layer; and an emitter electrode overlays the inter-polysilicon dielectric layer and the emitter region. The doped inter-polysilicon dielectric layer is the dopant source for forming the extrinsic base region and the base link-up region.

摘要翻译： 双极晶体管包括集电极区域，集电极区域内的本征基极区域，集电极区域内的非本征基极区域。 以及在本征基极区域和外部基极区域之间的集电极区域内的基极连接区域。 发射极区域位于本征基区内。 基极覆盖并与外部基极区域和基极连接区域的一部分电连通，并且掺杂的多晶硅间介电层覆盖基极的一部分。 覆盖层位于多晶硅间介质层的上方; 并且发射极电极覆盖多晶硅间介质层和发射极区域。 掺杂的多晶硅间介质层是用于形成外部基极区域和基极连接区域的掺杂剂源。

公开(公告)号：US06239477B1

公开(公告)日：2001-05-29

申请号：US09167855

申请日：1998-10-07

申请人： F. Scott Johnson

发明人： F. Scott Johnson

IPC分类号： H01L27082

CPC分类号： H01L29/66287 ,  H01L21/28518 ,  H01L21/28525

摘要： An emitter contact structure, and associated method, for a bipolar junction transistor. The emitter contact structure includes a collector region, an intrinsic base region within the collector region, an extrinsic base region within the collector region, a base link-up region within the collector region between the intrinsic base region and the extrinsic base region, a base link diffusion source layer above the base link-up region, a capping layer above the base link diffusion source layer, and a base electrode laterally engaging the extrinsic base region.

摘要翻译： 用于双极结型晶体管的发射极接触结构和相关方法。 发射极接触结构包括集电极区域，集电极区域内的本征基极区域，集电极区域内的非本征基极区域，在本征基极区域和外部基极区域之间的集电极区域内的基极连接区域， 基极连接区域上方的连接扩散源层，基极扩散源层上方的覆盖层和横向接合外部基极区域的基极。

公开(公告)号：US20060270139A1

公开(公告)日：2006-11-30

申请号：US11462528

申请日：2006-08-04

申请人： F. Scott Johnson ,  Tad Grider ,  Benjamin McKee

发明人： F. Scott Johnson ,  Tad Grider ,  Benjamin McKee

IPC分类号： H01L21/8238

CPC分类号： H01L21/26513 ,  H01L21/28035 ,  H01L21/324 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted into the exposed gate structure.

摘要翻译： 公开了用于半导体器件制造的方法，其中将掺杂剂选择性地注入到晶体管栅极结构中以抵消或补偿在随后的制造处理期间的掺杂剂耗尽。 图案化的注入掩模形成在半导体器件上，其暴露栅极结构的至少一部分并且覆盖器件的剩余上表面。 此后，将掺杂剂选择性地注入到暴露的栅极结构中。

公开(公告)号：US07098098B2

公开(公告)日：2006-08-29

申请号：US10226536

申请日：2002-08-23

申请人： F. Scott Johnson ,  Tad Grider ,  Benjamin P. Mckee

发明人： F. Scott Johnson ,  Tad Grider ,  Benjamin P. Mckee

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/04

CPC分类号： H01L29/66545 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/324 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted into the exposed gate structure.

公开(公告)号：US06501152B1

公开(公告)日：2002-12-31

申请号：US09371645

申请日：1999-08-10

申请人： F. Scott Johnson

发明人： F. Scott Johnson

IPC分类号： H01L2900

CPC分类号： H01L29/6625 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/735

摘要： A lateral NPN transistor (LPNP) (102) having the lightly doped drain extension implant blocked from the emitter region (118) but not the collector region (120). Accordingly, the emitter region (118) has a more abrupt junction for high emitter injection efficiency while the collector region (120) has a lightly doped region for reduced base depletion.

摘要翻译： 具有轻掺杂漏极延伸注入的横向NPN晶体管（LPNP）（102）从发射极区域（118）而不是集电极区域（120）阻挡。 因此，发射极区域（118）具有更高的发射极注入效率的突变结，而集电极区域（120）具有用于减少碱基耗尽的轻掺杂区域。

公开(公告)号：US06194280B1

公开(公告)日：2001-02-27

申请号：US09262389

申请日：1999-03-04

申请人： F. Scott Johnson

发明人： F. Scott Johnson

IPC分类号： H01L21331

CPC分类号： H01L29/66272

摘要： A bipolar transistor includes a collector region, an intrinsic base region within the collector region, an extrinsic base region within the collector region, and a base link-up region within the collector region between the intrinsic base region and the extrinsic base region. An emitter region is positioned within the intrinsic base region. A base electrode overlays and is in electrical communication with a portion of the extrinsic base region and the base link-up region, and a doped inter-polysilicon dielectric layer overlays a portion of the base electrode. A capping layer is positioned above the inter-polysilicon dielectric layer; and an emitter electrode overlays the inter-polysilicon dielectric layer and the emitter region. The doped inter-polysilicon dielectric layer is the dopant source for forming the extrinsic base region and the base link-up region.

摘要翻译： 双极晶体管包括集电极区域，集电极区域内的本征基极区域，集电极区域内的非本征基极区域，以及在本征基极区域和外部基极区域之间的集电极区域内的基极连接区域。 发射极区域位于本征基区内。 基极覆盖并与外部基极区域和基极连接区域的一部分电连通，并且掺杂的多晶硅间介电层覆盖基极的一部分。 覆盖层位于多晶硅间介质层的上方; 并且发射极电极覆盖多晶硅间介质层和发射极区域。 掺杂的多晶硅间介质层是用于形成外部基极区域和基极连接区域的掺杂剂源。