公开(公告)号：US20110154170A1

公开(公告)日：2011-06-23

申请号：US12973792

申请日：2010-12-20

申请人： Raghu N. Challa ,  Thomas B. Wilborn ,  Supratik Bhattacharjee

发明人： Raghu N. Challa ,  Thomas B. Wilborn ,  Supratik Bhattacharjee

IPC分类号： H03M13/09 ,  G06F11/10

CPC分类号： H04L1/1635 ,  H03M13/09 ,  H03M13/2957 ,  H03M13/6525 ,  H04L1/0053 ,  H04L1/0061 ,  H04L1/06 ,  H04L1/1806 ,  H04L1/1829

摘要： Methods, apparatus and articles of manufacture are disclosed that provide for early termination based on transport block fail for acknowledgement bundling in time division duplex. In one embodiment, a method for operating a communication device is provided. In this embodiment, the communication device decodes a downlink subframe that is part of a bundle of subframes. If it detects a CRC failure in the subframe, it inhibits decoding of at least one other subframe in the bundle if present and reports the failure to the sending node. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the disclosed subject matter. Therefore, it is to be understood that it should not be used to interpret or limit the scope or the meaning of the claims.

摘要翻译： 公开了基于传输块故障的提前终止的方法，装置和制品，用于在时分双工中进行确认捆绑。 在一个实施例中，提供了一种用于操作通信设备的方法。 在该实施例中，通信设备对作为一组子帧的一部分的下行链路子帧进行解码。 如果它检测到子帧中的CRC故障，则它阻止对捆绑中的至少一个其他子帧的解码（如果存在），并将该故障报告给发送节点。 本摘要仅用于遵守允许读者快速确定所披露的主题的抽象要求规则。 因此，应当理解，它不应用于解释或限制权利要求书的范围或含义。

公开(公告)号：US20090304116A1

公开(公告)日：2009-12-10

申请号：US12408603

申请日：2009-03-20

申请人： Raghu N. Challa ,  Hemanth Sampath ,  Gwendolyn D. Barriac

发明人： Raghu N. Challa ,  Hemanth Sampath ,  Gwendolyn D. Barriac

IPC分类号： H04L27/06

CPC分类号： H04L25/03019 ,  H04L2025/03426 ,  H04L2025/03726

摘要： An apparatus including a configurable demodulation architecture which includes a control module and a demodulation engine. The control module includes a set of one or more control fields. The demodulation engine includes a spatial whitening module, a Minimum Mean Square Estimation (MMSE) module, at least a first Maximal Ratio Combining (MRC) module, and at least one multiplexer. Further, the multiplexer is coupled to the instruction module and controlled based on the control fields to select at least one of the MMSE module or MRC module.

摘要翻译： 一种包括可配置解调架构的装置，其包括控制模块和解调引擎。 控制模块包括一组一个或多个控制域。 解调引擎包括空间白化模块，最小均方估计（MMSE）模块，至少第一最大比组合（MRC）模块和至少一个多路复用器。 此外，多路复用器耦合到指令模块并且基于控制字段来控制，以选择MMSE模块或MRC模块中的至少一个。

公开(公告)号：US08780768B2

公开(公告)日：2014-07-15

申请号：US13069296

申请日：2011-03-22

申请人： Raghu N. Challa ,  Brian Clarke Banister

发明人： Raghu N. Challa ,  Brian Clarke Banister

IPC分类号： H04J3/06

CPC分类号： H03G3/3078

摘要： In embodiments, user equipment (UE) is configured to acquire automatic gain control (AGC) of an analog RF front end by maintaining a plurality of M×N AGC loops in which the output of the power detector drives input of a gain state machine after a predetermined delay. Each of the loops corresponds to a different periodic set of tasks of (1/M) subframe in length. In each of the loops, the gain is determined by a power measurement taken ((M×N)+1) tasks ago. A synchronization signal, such as a Primary Synchronization Signal, occurs early in Time Division Duplex (TDD) subframes that follow selected downlink subframes. The periodicity of the selected subframes is N. This allows the UE to converge on proper AGC gain for downlink subframes through a relatively short search, such as a binary search. The UE can then decode the synchronization signal and acquire network timing.

摘要翻译： 在实施例中，用户设备（UE）被配置为通过维持多个M×N个AGC环路来获取模拟RF前端的自动增益控制（AGC），其中功率检测器的输出驱动增益状态机的输入驱动增益状态机的输入， 预定的延迟。 每个循环对应于长度为（1 / M）子帧的不同周期性任务集合。 在每个循环中，增益由以前进行的功率测量（（M×N）+1）任务确定。 诸如主同步信号的同步信号早于在选择的下行链路子帧之后的时分双工（TDD）子帧中。 所选择的子帧的周期为N.这允许UE通过相对较短的搜索（例如二进制搜索）收敛于针对下行链路子帧的适当的AGC增益。 然后，UE可以对同步信号进行解码并获取网络定时。

公开(公告)号：US08738680B2

公开(公告)日：2014-05-27

申请号：US12411728

申请日：2009-03-26

申请人： Arunava Chaudhuri ,  Hemanth Sampath ,  Iwen Yao ,  Jeremy H. Lin ,  Raghu N. Challa ,  Min Wu

发明人： Arunava Chaudhuri ,  Hemanth Sampath ,  Iwen Yao ,  Jeremy H. Lin ,  Raghu N. Challa ,  Min Wu

IPC分类号： G06F17/14

CPC分类号： G06F17/142 ,  H04L5/0007 ,  H04L5/0023 ,  H04L5/0053 ,  H04L27/265 ,  H04L27/2662

摘要： An improved processing engine for performing Fourier transforms includes an instruction processor configured to process sequential instruction software commands and a Fourier transform engine coupled to the instruction processor. The Fourier transform engine is configured to perform Fourier transforms on a serial stream of data. The Fourier transform engine is configured to receive configuration information and operational data from the instruction processor via a set of software tasks.

摘要翻译： 用于执行傅里叶变换的改进的处理引擎包括配置成处理顺序指令软件命令的指令处理器和耦合到指令处理器的傅里叶变换引擎。 傅立叶变换引擎被配置为对串行数据流执行傅里叶变换。 傅里叶变换引擎被配置为经由一组软件任务从指令处理器接收配置信息和操作数据。

公开(公告)号：US08576955B2

公开(公告)日：2013-11-05

申请号：US12413069

申请日：2009-03-27

申请人： Raghu N. Challa ,  Hemanth Sampath ,  Ali RostamPisheh

发明人： Raghu N. Challa ,  Hemanth Sampath ,  Ali RostamPisheh

IPC分类号： H04L27/06

CPC分类号： H04L1/0045 ,  H03M13/2957 ,  H03M13/6566 ,  H04L5/0007 ,  H04L27/2647

摘要： An apparatus and method for enhanced downlink processing of received channels in a mobile communications system is described, containing a buffer for control data and traffic data, a demapper engine with at least two independently operating demappers for demapping the control and traffic data, a log-likelihood-ratio (LLR) buffer for supporting memory segments accessible by the demapper engine, a decoder engine containing decoders, each of the decoders operating on data from selected memory segment(s) of the LLR buffer, and an arbitrator providing control of at least one of the demapper engine, LLR buffer, and decoder engine. At least one of the decoders is suited for decoding control data and another one of the decoders is suited for decoding traffic data. By partitioning the decoding as such, an increase in downlink throughput can be obtained.

摘要翻译： 描述了一种用于在移动通信系统中增强接收信道的下行链路处理的装置和方法，其包括用于控制数据和业务数据的缓冲器，具有至少两个独立操作的解映射器的解映射器引擎，用于对所述控制和业务数据进行解映射， 用于支持由解映射器引擎可访问的存储器段的似然比（LLR）缓冲器，包含解码器的解码器引擎，每个解码器对来自所选择的LLR缓冲器的所选存储器段的数据进行操作，以及至少提供至少控制的仲裁器 一个解映射引擎，LLR缓冲区和解码引擎。 解码器中的至少一个适合于解码控制数据，并且解码器中的另一个适合于解码业务数据。 通过分解解码，可以获得下行链路吞吐量的增加。

公开(公告)号：US20100322117A1

公开(公告)日：2010-12-23

申请号：US12796009

申请日：2010-06-08

申请人： Remi J. Gurski ,  Raghu N. Challa ,  Matthias Brehler

发明人： Remi J. Gurski ,  Raghu N. Challa ,  Matthias Brehler

IPC分类号： H04J3/00

CPC分类号： H03G3/3078 ,  H03G3/3042 ,  H03G3/3052 ,  H04B1/70735 ,  H04B1/708

摘要： Disclosed are methods and apparatus for initial acquisition in a communication system, and in particular Time Division Duplex (TDD) systems such as those found in LTE. A disclosed method, for example, includes running a plurality of predetermined amplifier gain states for a low noise amplifier (LNA) during initial acquisition in a time division duplex (TDD) system, and determining acquisition of a received signal based on searching across the plurality of predetermined amplifier gain states. Forcing the amplifier gain into a set of predetermined gain states affords quicker resolution of initial acquisition for setting the gain of the LNA, which in TDD systems is complicated due to an uncertain uplink/downlink timeline that precludes continuous operation of a gain setting algorithm run in the LNA.

摘要翻译： 公开了用于在通信系统中的初始采集的方法和装置，特别是诸如在LTE中发现的时分双工（TDD）系统。 所公开的方法例如包括在时分双工（TDD）系统中的初始采集期间运行用于低噪声放大器（LNA）的多个预定的放大器增益状态，以及基于跨越多个的搜索来确定接收信号的获取 的预定放大器增益状态。 将放大器增益强制为一组预定增益状态可以提供更快的初始采集分辨率，用于设置LNA的增益，由于不确定的上行链路/下行链路时间轴，TDD系统复杂，导致增加设置算法持续运行， LNA。

公开(公告)号：US20090249134A1

公开(公告)日：2009-10-01

申请号：US12404613

申请日：2009-03-16

申请人： Ali RostamPisheh ,  Raghu N. Challa ,  Iwen Yao ,  Davie J. Santos ,  Mrinal M. Nath

发明人： Ali RostamPisheh ,  Raghu N. Challa ,  Iwen Yao ,  Davie J. Santos ,  Mrinal M. Nath

IPC分类号： G11C29/00 ,  G06F12/02

CPC分类号： H03M13/2785 ,  H03M13/2764 ,  H03M13/2771 ,  H03M13/2775 ,  H03M13/6566

摘要： A de-interleaver generates a plurality of De-interleaved Reorder Physical (DRP) addresses to simultaneously write a corresponding plurality of LLR values into a multi-banked memory such that not more than one LLR value is written into each bank of the multi-banked memory at a time. A sequence of such parallel writes results in the LLR values of a transmission of a sub-packet being stored in the memory. Address translation performed during generation of the DRP addresses causes the LLR values to be stored within the banks such that a decoder can read LLR values out of the memory in a de-interleaved sequence. Each memory location of a bank is a word-location for storing multiple related LLR values, where one LLR value is stored along with its parity values. The ability to simultaneously write to multiple LLR values is used to clear locations in a fast and efficient manner.

摘要翻译： 解交织器生成多个解交织重排物理（DRP）地址，以将对应的多个LLR值同时写入多存储存储器，使得不多于一个LLR值被写入多存储体的每个存储体 一次记忆 这种并行写入的序列导致存储在存储器中的子包的传输的LLR值。 在生成DRP地址期间执行的地址转换导致LLR值被存储在存储体中，使得解码器可以以解交织的顺序读出存储器中的LLR值。 存储体的每个存储器位置是用于存储多个相关LLR值的字位置，其中一个LLR值与其奇偶校验值一起存储。 用于同时写入多个LLR值的能力用于以快速有效的方式清除位置。

公开(公告)号：US09071493B2

公开(公告)日：2015-06-30

申请号：US12824958

申请日：2010-06-28

申请人： Brian C. Banister ,  Shivratna G. Srinivasan ,  Matthias Brehler ,  Sunil Kumar Kandukuri Narayana ,  Raghu N. Challa

发明人： Brian C. Banister ,  Shivratna G. Srinivasan ,  Matthias Brehler ,  Sunil Kumar Kandukuri Narayana ,  Raghu N. Challa

IPC分类号： H03D3/24 ,  H04L27/26 ,  H03J1/00 ,  H04L27/00

CPC分类号： H04L27/2657 ,  H03J1/005 ,  H04L2027/0055 ,  H04L2027/0065 ,  H04L2027/0067

摘要： Methods and apparatus for correcting frequency errors between a carrier frequency of a signal received by a wireless device and a reference frequency local to the device. For certain aspects, such a method generally includes receiving a signal in a receiver having an LO producing a reference frequency, a radio frequency (RF) phase-locked loop (PLL), and a digital rotator, estimating a frequency difference between a carrier frequency of the received signal and the LO reference frequency, and applying the estimated frequency difference to the RF PLL and the digital rotator.

摘要翻译： 用于校正由无线设备接收的信号的载波频率与设备本地的参考频率之间的频率误差的方法和装置。 对于某些方面，这种方法通常包括在具有产生参考频率的LO的接收机中接收信号，射频（RF）锁相环（PLL）和数字旋转器，估计载波频率 的接收信号和LO参考频率，并将估计的频差应用于RF PLL和数字旋转器。

公开(公告)号：US08995590B2

公开(公告)日：2015-03-31

申请号：US12408603

申请日：2009-03-20

申请人： Raghu N. Challa ,  Hemanth Sampath ,  Gwendolyn D. Barriac

发明人： Raghu N. Challa ,  Hemanth Sampath ,  Gwendolyn D. Barriac

IPC分类号： H04L27/06 ,  H04L25/03

CPC分类号： H04L25/03019 ,  H04L2025/03426 ,  H04L2025/03726

摘要： An apparatus including a configurable demodulation architecture which includes a control module and a demodulation engine. The control module includes a set of one or more control fields. The demodulation engine includes a spatial whitening module, a Minimum Mean Square Estimation (MMSE) module, at least a first Maximal Ratio Combining (MRC) module, and at least one multiplexer. Further, the multiplexer is coupled to the instruction module and controlled based on the control fields to select at least one of the MMSE module or MRC module.

摘要翻译： 一种包括可配置解调架构的装置，其包括控制模块和解调引擎。 控制模块包括一组一个或多个控制域。 解调引擎包括空间白化模块，最小均方估计（MMSE）模块，至少第一最大比组合（MRC）模块和至少一个多路复用器。 此外，多路复用器耦合到指令模块并且基于控制字段来控制，以选择MMSE模块或MRC模块中的至少一个。

公开(公告)号：US08989061B2

公开(公告)日：2015-03-24

申请号：US12796009

申请日：2010-06-08

申请人： Remi J. Gurski ,  Matthias Brehler ,  Raghu N. Challa

发明人： Remi J. Gurski ,  Matthias Brehler ,  Raghu N. Challa

IPC分类号： H04J3/00 ,  H03G3/30 ,  H04B1/7073 ,  H04B1/708

CPC分类号： H03G3/3078 ,  H03G3/3042 ,  H03G3/3052 ,  H04B1/70735 ,  H04B1/708

摘要： A plurality of predetermined amplifier gain states for a low noise amplifier (LNA) are run during initial acquisition in a time division duplex (TDD) system. Acquisition of a received signal is determined based on searching across the plurality of predetermined amplifier gain states. Forcing the amplifier gain into a set of predetermined gain states affords quicker resolution of initial acquisition for setting the gain of the LNA, which in TDD systems is complicated due to an uncertain uplink/downlink timeline that precludes continuous operation of a gain setting algorithm run in the LNA.

摘要翻译： 在时分双工（TDD）系统的初始采集期间，运行低噪声放大器（LNA）的多个预定的放大器增益状态。 基于在多个预定的放大器增益状态中搜索来确定接收信号的获取。 将放大器增益强制为一组预定增益状态可以提供更快的初始采集分辨率，用于设置LNA的增益，由于不确定的上行链路/下行链路时间轴，TDD系统复杂，导致增加设置算法持续运行， LNA。