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公开(公告)号：US20200218669A1
公开(公告)日：2020-07-09
申请号：US16820630
申请日：2020-03-16
申请人： Ginger H. Gilsdorf , Karthik Kumar , Mark A. Schmisseur , Thomas Willhalm , Francesc Guim Bernat
发明人： Ginger H. Gilsdorf , Karthik Kumar , Mark A. Schmisseur , Thomas Willhalm , Francesc Guim Bernat
IPC分类号： G06F12/123 , G06F12/0891 , G06F12/02 , G06F1/14 , G11C7/22
摘要： An apparatus and/or system is described including a memory device including a memory range and a temporal data management unit (TDMU) coupled to the memory device to receive from an interface, the memory range and a temporal range corresponding to validity of data in the memory range, check the temporal range against a time and/or date value provided by a timer or clock to identify the data in the memory range as expired, and invalidate the data that is expired in the memory device. In some embodiments, the TDMU includes hardware logic that resides on a memory module with the memory device and is coupled to invalidate expired data when the memory module is decoupled from the interface. Other embodiments may be disclosed and claimed.
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公开(公告)号：US20200186592A1
公开(公告)日：2020-06-11
申请号：US16790342
申请日：2020-02-13
摘要： Methods and apparatus for scale out hardware-assisted tracing schemes for distributed and scale-out applications. In connection with execution of one or more applications using a distributed processing environment including multiple compute nodes, telemetry and tracing data are obtained using hardware-based logic on the compute nodes. Processes associated with applications are identified, as well as the compute nodes on which instances of the processes are executed. Process instances are associated with process application space identifiers (PASIDs), while processes used for an application are associating with a global group identifier (GGID) that serves as an application ID. The PASIDs and GGIDs are used to store telemetry and/or tracing data on the compute nodes and/or forward such data to a tracing server in a manner that enables telemetry and/or tracing data to be aggregated on an application basis. Telemetry and/or tracing data may be obtained from processors on the compute nodes, and (optionally) additional elements such as network interface controllers (NICs). Tracing data may also be obtained from switches used for forwarding data between processes.
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公开(公告)号：US11343177B2
公开(公告)日：2022-05-24
申请号：US17086320
申请日：2020-10-30
IPC分类号： H04L12/725 , H04L45/302 , H04L47/125 , H04L49/10 , H04L47/26 , H04L49/20
摘要： Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.
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公开(公告)号：US20210109584A1
公开(公告)日：2021-04-15
申请号：US17132202
申请日：2020-12-23
摘要： Various aspects of methods, systems, and use cases include coordinating actions at an edge device based on power production in a distributed edge computing environment. A method may include identifying a long-term service level agreement (SLA) for a component of an edge device, and determining a list of resources related to the component using the long-term SLA. The method may include scheduling a task for the component based on the long-term SLA, a current battery level at the edge device, a current energy harvest rate at the edge device, or an amount of power required to complete the task. A resource of the list of resources may be used to initiate the task, such as according to the scheduling.
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15.发明申请公开(公告)号：US20190222518A1
公开(公告)日：2019-07-18
申请号：US16369430
申请日：2019-03-29
IPC分类号： H04L12/803 , H04L12/851 , H04L12/813 , H04L12/927 , H04L12/26
CPC分类号： H04L47/125 , H04L43/08 , H04L47/20 , H04L47/2425 , H04L47/805
摘要： Technologies for load balancing on a network device in an edge network are disclosed. According to one embodiment, a network device receives, in the edge network, a request to access a function. The request includes one or more performance requirements. The network device identifies, as a function of an evaluation of the performance requirements and on monitored properties of each device associated with the network device, one or more of the devices to service the request. The network device selects one of the identified devices according to a load balancing policy and sends the request to the selected device.
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16.发明申请公开(公告)号：US20180089044A1
公开(公告)日：2018-03-29
申请号：US15277522
申请日：2016-09-27
摘要： Technologies for providing network interface support for remote memory and storage failover protection include a compute node. The compute node includes a memory to store one or more protected resources and a network interface. The network interface is to receive, from a requestor node in communication with the compute node, a request to access one of the protected resources. The request identifies the protected resource by a memory address. Additionally, the network interface is to determine an identity of the requestor node and determine, as a function of the identity and permissions data associated with the memory address, whether the requestor node has permission to access the protected resource. Other embodiments are described and claimed.
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公开(公告)号：US20210064531A1
公开(公告)日：2021-03-04
申请号：US17092803
申请日：2020-11-09
IPC分类号： G06F12/0817
摘要： Methods and apparatus for software-defined coherent caching of pooled memory. The pooled memory is implemented in an environment having a disaggregated architecture where compute resources such as compute platforms are connected to disaggregated memory via a network or fabric. Software-defined caching policies are implemented in hardware in a processor SoC or discrete device such as a Network Interface Controller (NIC) by programming logic in an FPGA or accelerator on the SoC or discrete device. The programmed logic is configured to implement software-defined caching policies in hardware for effecting disaggregated memory (DM) caching in an associated DM cache of at least a portion of an address space allocated for the software application in the disaggregated memory. In connection with DM cache operations, such as cache lines evicted from a CPU, logic implemented in hardware determines whether a cache line in a DM cache is to be convicted and implements the software-defined caching policy for the DM cache including associated memory coherency operations.
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公开(公告)号：US20200026575A1
公开(公告)日：2020-01-23
申请号：US16586576
申请日：2019-09-27
IPC分类号： G06F9/50
摘要： Methods, apparatus, systems and machine-readable storage media of an edge computing device which is enabled to access and select the use of local or remote acceleration resources for edge computing processing is disclosed. In an example, an edge computing device obtains first telemetry information that indicates availability of local acceleration circuitry to execute a function, and obtains second telemetry that indicates availability of a remote acceleration function to execute the function. An estimated time (and cost or other identifiable or estimateable considerations) to execute the function at the respective location is identified. The use of the local acceleration circuitry or the remote acceleration resource is selected based on the estimated time and other appropriate factors in relation to a service level agreement.
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公开(公告)号：US20190041960A1
公开(公告)日：2019-02-07
申请号：US16011842
申请日：2018-06-19
申请人： Francesc Guim Bernat , Suraj Prabhakaran , Timothy Verrall , Karthik Kumar , Mark A. Schmisseur
发明人： Francesc Guim Bernat , Suraj Prabhakaran , Timothy Verrall , Karthik Kumar , Mark A. Schmisseur
摘要： In one embodiment, an apparatus of an edge computing system includes memory that includes instructions and processing circuitry coupled to the memory. The processing circuitry implements the instructions to process a request to execute at least a portion of a workflow on pooled computing resources, the workflow being associated with a particular tenant, determine an amount of power to be allocated to particular resources of the pooled computing resources for execution of the portion of the workflow based on a power budget associated with the tenant and a current power cost, and control allocation of the determined amount of power to the particular resources of the pooled computing resources during execution of the portion of the workflow.
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公开(公告)号：US20230006889A1
公开(公告)日：2023-01-05
申请号：US17900653
申请日：2022-08-31
IPC分类号： H04L41/122 , H04L41/5025
摘要： The present disclosure is generally related to edge computing technologies (ECTs), communications networking, network slicing, and in particular, to techniques and technologies for providing flow-specific network slices. In particular, the present disclosure describes mechanisms that expand existing end-to-end architectures in order to include quality of service and monitoring mechanisms that connect network slicing technologies with infrastructure and/or network data center quality of service provider domains. The described mechanisms provide data center bridging to enable network, edge computing, and cloud computing domains.
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