公开(公告)号：US07872894B2

公开(公告)日：2011-01-18

申请号：US12421821

申请日：2009-04-10

Applicant: Philippe Roche ,  Francois Jacquet

Inventor： Philippe Roche ,  Francois Jacquet

IPC: G11C5/06

CPC classification number: G11C11/4125 ,  G11C5/005

Abstract: A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage spike which modifies the information in one of the nodes of the pair using the information stored in the other node. The data storage nodes of each pair in the cell are implanted on opposite sides of an opposite conductivity type well from one another within a region of a substrate defining the boundaries of the memory cell.

Abstract translation: 存储器单元被保护以防止电流或电压尖峰。 小区包括用于在至少一对互补节点中存储信息的一组冗余数据存储节点。 小区还包括用于在当前或电压尖峰之后将信息恢复到其初始状态的电路，其使用存储在另一节点中的信息来修改对中的一个节点中的信息。 单元中每对的数据存储节点在限定存储单元的边界的衬底的区域内相互注入相对导电类型的相对侧。

公开(公告)号：US20080049524A1

公开(公告)日：2008-02-28

申请号：US11844025

申请日：2007-08-23

Applicant: Gilles Gasiot ,  Francois Jacquet ,  Philippe Roche

Inventor： Gilles Gasiot ,  Francois Jacquet ,  Philippe Roche

IPC: G11C7/00

CPC classification number: G11C11/4125

Abstract: A memory cell stores information in the form of a first logic level and a second logic level that are complementary to each other. The memory cell includes a first storage circuit and a second storage circuit for storing the first logic level and the second logic level. The first and second storage circuits each have a respective input and output. An isolation circuit provides electrical isolation of the input of the first storage device from the output of the second storage device, except during access to the first and second storage circuits.

Abstract translation: 存储器单元以彼此互补的第一逻辑电平和第二逻辑电平的形式存储信息。 存储单元包括用于存储第一逻辑电平和第二逻辑电平的第一存储电路和第二存储电路。 第一和第二存储电路各自具有相应的输入和输出。 除了在访问第一和第二存储电路期间，隔离电路提供第一存储装置的输入与第二存储装置的输出的电隔离。

公开(公告)号：US20070216464A1

公开(公告)日：2007-09-20

申请号：US11713469

申请日：2007-03-01

Applicant: Philippe Roche ,  Francois Jacquet ,  Jean-Jacques De Jong

Inventor： Philippe Roche ,  Francois Jacquet ,  Jean-Jacques De Jong

IPC: G06F1/04

CPC classification number: H03K19/00338 ,  G06F1/10 ,  G06F1/24 ,  H03K5/1506

Abstract: An embodiment of the invention relates to a circuit for distributing an initial signal, comprising an input node receiving the initial signal, a plurality of terminal nodes each providing at least one resulting signal to a circuit component, and different connection branches between the input node and the plurality of terminal nodes, to which a plurality of intermediate nodes is connected, wherein connection branch is duplicated, so that each node among the input node and the intermediate nodes comprises two inputs and two outputs allowing double propagation of the initial signal towards the terminal nodes through duplicated connection branches, each terminal node terminal node receiving two input signals, images of the initial signal and providing the resulting initial signal: an image of the input signals if said input signals are identical, or inactive, if the input signals are different from each other.

Abstract translation: 本发明的一个实施例涉及一种用于分发初始信号的电路，包括接收初始信号的输入节点，每个向电路组件提供至少一个结果信号的多个终端节点，以及输入节点和 连接多个中间节点的多个终端节点，其中连接分支被复制，使得输入节点和中间节点之间的每个节点包括两个输入和两个输出，允许初始信号向终端双重传播 节点通过重复连接分支，每个终端节点终端节点接收两个输入信号，初始信号的图像并提供所得到的初始信号：如果所述输入信号相同或不活动，则输入信号的图像如果输入信号不同 从彼此。

公开(公告)号：US20070057700A1

公开(公告)日：2007-03-15

申请号：US11428471

申请日：2006-07-03

Applicant: Francois Jacquet ,  Thierry Devoivre

Inventor： Francois Jacquet ,  Thierry Devoivre

IPC: H03K5/22

CPC classification number: G11C15/04

Abstract: A content addressable memory (CAM) includes first and second memory circuits and a comparison circuit. The first memory circuit includes first and second sets of transistors for the storage of first and second compare data. The second memory circuit includes first and second sets of transistors for the storage of enabling or disabling data. The comparison circuit includes first and second sets of comparison transistors which respectively provide for the comparison of the first and second compare data with first and second input data under the control of an output signal from the second memory circuit. The transistors of the first and second sets of transistors of the memory circuits each includes a transistor of a first conductivity type and a transistor of a second conductivity type. The transistors of the second conductivity type are formed on the same first active zone of the semiconductor substrate. The first and second sets of comparison transistors of the comparison circuit are formed in separate active zones, respectively, which are mutually separated by the first active zone.

Abstract translation: 内容可寻址存储器（CAM）包括第一和第二存储器电路和比较电路。 第一存储器电路包括用于存储第一和第二比较数据的第一和第二组晶体管。 第二存储器电路包括用于存储启用或禁用数据的第一和第二组晶体管。 比较电路包括在第二存储器电路的输出信号的控制下分别提供第一和第二比较数据与第一和第二输入数据的比较的第一组和第二组比较晶体管。 存储电路的第一和第二组晶体管的晶体管各自包括第一导电类型的晶体管和第二导电类型的晶体管。 第二导电类型的晶体管形成在半导体衬底的相同的第一有源区上。 比较电路的第一组和第二组比较晶体管分别形成在由第一有源区相互隔开的分离的有源区中。

公开(公告)号：US20060171183A1

公开(公告)日：2006-08-03

申请号：US11048224

申请日：2005-02-01

Applicant: Mark Lysinger ,  Francois Jacquet ,  Phillippe Roche

Inventor： Mark Lysinger ,  Francois Jacquet ,  Phillippe Roche

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: A Content Addressable Memory (CAM) circuit includes memory cells preferably formed as two memory cells each having internal nodes. A compare circuit is operative with the memory cells. A common terminal (VPL) exists for the memory cells. Capacitors are added between the internal nodes of each of the memory cells and common terminal for memory cell stability.

Abstract translation: 内容可寻址存储器（CAM）电路包括优选地形成为具有内部节点的两个存储器单元的存储器单元。 比较电路与存储器单元一起工作。 存储单元存在公共端（VPL）。 在每个存储单元的内部节点和公共端子之间添加电容器用于存储器单元的稳定性。

公开(公告)号：US20060056230A1

公开(公告)日：2006-03-16

申请号：US11225887

申请日：2005-09-12

Applicant: Francois Jacquet ,  Philippe Roche

Inventor： Francois Jacquet ,  Philippe Roche

IPC: G11C7/10 ,  G11C11/00

CPC classification number: H03K3/35625 ,  H03K3/0375 ,  H03K3/356156

Abstract: A multivibrator includes a first data transfer port that receives, as input, multivibrator input data. A first, master, latch cell is connected on the output side of the first transfer port. A second, slave, latch cell is connected thereto through a second data transfer port placed between the first and second latch cells. Each latch cell includes a set of redundant data storage nodes for storing information in at least one pair of complementary nodes and circuitry for restoring information in its initial state, after a current or voltage spike has modified the information in one of the nodes of the said pair, on the basis of the information stored in the other node. The nodes of each pair are implanted opposite one another in a zone of a substrate defining the latch cell.

Abstract translation: 多谐振荡器包括接收多谐振荡器输入数据作为输入的第一数据传送端口。 第一个主锁存单元连接在第一个传输端口的输出侧。 第二个从锁存单元通过位于第一和第二锁存单元之间的第二数据传送端口连接到其上。 每个锁存单元包括一组用于在至少一对互补节点中存储信息的冗余数据存储节点和用于在其初始状态中恢复信息的电路，在电流或电压尖峰已经修改了所述第一个节点中的一个节点中的信息 对，基于存储在另一个节点中的信息。 每对的节点在限定锁存单元的衬底的区域中彼此相对植入。

公开(公告)号：US20050184325A1

公开(公告)日：2005-08-25

申请号：US10877755

申请日：2004-06-25

Applicant: Francois Jacquet ,  Philippe Candellier ,  Robin Cerutti ,  Philippe Coronel ,  Pascale Mazoyer

Inventor： Francois Jacquet ,  Philippe Candellier ,  Robin Cerutti ,  Philippe Coronel ,  Pascale Mazoyer

IPC: G11C11/405 ,  H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  H01L29/76

CPC classification number: H01L27/0688 ,  G11C11/405 ,  H01L27/108

Abstract: An integrated dynamic random access memory element includes two cells for the storage of two respective bits. A source region and a drain region are included. Each cell comprises a field-effect transistor having a gate and an intermediate portion which extend between the source and drain regions. A channel is provided in the intermediate portion of the transistor for each cell. A polarization electrode is placed between the respective intermediate portions of the two transistors. This polarization electrode is capacitively coupled to the intermediate portion of each transistor and is used to store the first and second bits.

Abstract translation: 集成的动态随机存取存储器元件包括两个用于存储两个相应位的单元。 包括源区和漏区。 每个单元包括具有栅极和在源极和漏极区域之间延伸的中间部分的场效应晶体管。 在每个单元的晶体管的中间部分设置有沟道。 偏振电极被放置在两个晶体管的各个中间部分之间。 该极化电极电容耦合到每个晶体管的中间部分，并用于存储第一和第二位。

公开(公告)号：US20050157534A1

公开(公告)日：2005-07-21

申请号：US10627955

申请日：2003-07-25

Applicant: Richard Ferrant ,  Francois Jacquet

Inventor： Richard Ferrant ,  Francois Jacquet

IPC: G11C11/406 ,  G11C11/24

CPC classification number: G11C11/406

Abstract: A DRAM including an array of storage elements arranged in lines and columns, and for each column: write means adapted to biasing at least a selected one of the elements to a charge level chosen from among a first predetermined high level and a second predetermined low level, combined with read circuitry adapted to determining whether the stored charge level is greater or smaller than a predetermined charge level; and isolation circuitry adapted to isolating the array from the read and/or write means, each column further including refreshment means, distinct from the read and write circuit, for increasing, beyond the first and second predetermined levels, the charge stored in a storage element.

Abstract translation: 一种DRAM，包括排列成行和列的存储元件的阵列，并且用于每列：写入装置，其适于将至少一个所选元素偏置到从第一预定高电平和第二预定低电平中选择的电荷电平 与读取电路组合，适于确定所存储的电荷电平是否大于或小于预定电荷电平; 以及隔离电路，其适于将阵列与读取和/或写入装置隔离，每列还包括与读取和写入电路不同的刷新装置，用于在第一和第二预定级别之外增加存储在存储元件中的电荷 。

公开(公告)号：US08593818B2

公开(公告)日：2013-11-26

申请号：US12912931

申请日：2010-10-27

Applicant: Francois Jacquet

Inventor： Francois Jacquet

IPC: H05K1/00

CPC classification number: G06F15/7825

Abstract: The present invention relates to a Network on chip comprising a torus matrix of processing elements formed by a juxtaposition of bricks in rows and columns, each brick comprising a longitudinal extra-connection bus segment connecting two terminals situated on opposite transverse edges of the brick on a first axis; two longitudinal intra-connection bus segments connecting circuits of the brick to respective terminals situated on the opposite transverse edges on a second axis symmetrical to the first axis with respect to the center of the brick; a transverse extra-connection bus segment connecting two terminals situated on opposite longitudinal edges of the brick on a third axis; and two transverse intra-connection bus segments connecting circuits of the brick to respective terminals situated on the opposite longitudinal edges on a fourth axis symmetrical to the third axis with respect to the center of the brick. The bricks are oriented at 180° from one to the next in the direction of the columns and in the direction of the rows, and each brick comprises an even number of power supply conductor segments arranged symmetrically with respect to an axis of symmetry of the brick and connecting opposite edges of the brick.

Abstract translation: 本发明涉及一种包括由行和列中的砖并置形成的处理元件的环面矩阵，每个砖包括连接位于砖的相对横向边缘上的两个端子的纵向附加连接总线段 第一轴; 两个纵向连接内总线段将砖的电路连接到相对于砖的中心对称于第一轴线的第二轴上相对的横向边缘上的相应端子; 连接位于第三轴上的砖的相对纵向边缘上的两个端子的横向额外连接总线段; 以及两个横向连接内总线段，其将砖的电路连接到位于相对于砖的中心与第三轴线对称的第四轴线的相对纵向边缘上的相应端子。 砖在列的方向和排列方向上从一个到另一个180°定向，并且每个砖包括相对于砖的对称轴对称布置的偶数个电源导体段 并连接砖的相对边缘。

公开(公告)号：US08335121B2

公开(公告)日：2012-12-18

申请号：US12829675

申请日：2010-07-02

Applicant: Cyrille Dray ,  Francois Jacquet ,  Sébastien Barasinski

Inventor： Cyrille Dray ,  Francois Jacquet ,  Sébastien Barasinski

IPC: G11C7/02

CPC classification number: G11C11/413

Abstract: A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.

Abstract translation: 提供了一种用于SRAM存储器信息存储的设备和相应的实现方法。 该设备由电源电压供电并且包括组合在基列中的基本单元的阵列，以及至少一个反射镜单元的至少一个反射镜列，其容易模拟基极柱中的单元的行为。 该装置还包括在立柱中的最大限制单元的反射镜列中的仿真装置，用于改变反射镜列的反射镜电源电压的装置和用于复制仿真基色列中的反射镜电源电压的装置。