公开(公告)号：US5753540A

公开(公告)日：1998-05-19

申请号：US699867

申请日：1996-08-20

Applicant: Koucheng Wu ,  Ivan Sanchez ,  Yu-Pin Han ,  Ying-Tsong Loh

Inventor： Koucheng Wu ,  Ivan Sanchez ,  Yu-Pin Han ,  Ying-Tsong Loh

IPC: H01L23/525 ,  H01L21/82

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: Disclosed is a method for programming an antifuse structure. The antifuse structure is programmed by applying an alternating current having alternating current pulses between a bottom and a top electrode to generate a conduction path through an antifuse material sandwiched between the electrodes. The conduction path is formed incrementally due to an electron flow produced as a result of each alternating current pulse thereby defining the conduction path at a substantially centered portion of the antifuse material.

Abstract translation: 公开了一种用于编程反熔丝结构的方法。 反熔丝结构通过在底部和顶部电极之间施加具有交流电脉冲的交流电来编程，以产生穿过夹在电极之间的反熔丝的导电路径。 由于由于每个交流脉冲而产生的电子流，传导路径增量地形成，从而在反熔丝材料的基本中心部分处限定导电路径。

公开(公告)号：US5821136A

公开(公告)日：1998-10-13

申请号：US698129

申请日：1996-08-15

Applicant: Tsiu Chiu Chan ,  Yu-Pin Han ,  Elmer H. Guritz ,  Richard A. Blanchard

Inventor： Tsiu Chiu Chan ,  Yu-Pin Han ,  Elmer H. Guritz ,  Richard A. Blanchard

IPC: H01L21/8244 ,  H01L27/06 ,  H01L27/092 ,  H01L27/11 ,  H01L21/00 ,  H01L21/84

CPC classification number: H01L27/11 ,  H01L27/0605 ,  H01L27/0922 ,  H01L27/1104 ,  H01L27/1108 ,  Y10S257/903 ,  Y10S438/981

Abstract: A CMOS device architecture which includes substrate-gated inverted PMOS transistors, as well as bulk NMOS. The inverted-PMOS channels are formed in a different layer from the NMOS gates, and these layers may even have different compositions. Moreover, the NMOS and inverted-PMOS devices have different gate oxide layers, so the thicknesses can be independently optimized. The drain underlap of the inverted device is defined by a patterning step, so it can be increased for high-voltage operation if desired.

Abstract translation: 一种CMOS器件架构，包括基板门控反相PMOS晶体管，以及体NMOS。 反向PMOS沟道形成在与NMOS栅极不同的层中，并且这些层甚至可以具有不同的组成。 此外，NMOS和反向PMOS器件具有不同的栅极氧化物层，因此可以独立优化厚度。 倒置器件的漏极叠层由图案化步骤限定，因此如果需要，可以增加高压操作。

公开(公告)号：US5783467A

公开(公告)日：1998-07-21

申请号：US582844

申请日：1995-12-29

Applicant: Yu-Pin Han ,  Ying-Tsong Loh ,  Ivan Sanchez

Inventor： Yu-Pin Han ,  Ying-Tsong Loh ,  Ivan Sanchez

IPC: H01L21/8246 ,  H01L27/112 ,  H01L21/82

CPC classification number: H01L27/11206 ,  H01L27/112

Abstract: An antifuse structure includes a first electrode, a layer of enhanced amorphous silicon over the first electrode, and a second electrode over the layer of enhanced amorphous silicon. The layer of enhanced amorphous silicon is formed by an ion-implantation of a neutral species and a dopant species into a deposited layer of amorphous silicon, such that the antifuse structure will have a stable conductive link in a programmed state and such that it will be less susceptible to off-state leakage in an unprogrammed state. A method for making an antifuse structure includes forming a lower electrode, depositing an amorphous silicon layer over the lower electrode, ion-implanting a neutral species and a dopant species into the amorphous silicon layer, and forming an upper electrode over the amorphous silicon layer.

Abstract translation: 反熔丝结构包括第一电极，在第一电极上方的增强非晶硅层，以及增强非晶硅层上的第二电极。 通过将中性物质和掺杂剂物质的离子注入到非晶硅的沉积层中形成增强非晶硅层，使得反熔丝结构将在编程状态下具有稳定的导电链路，并且使得其将被 在非编程状态下较不易于断态泄漏。 制造反熔丝结构的方法包括形成下电极，在下电极上沉积非晶硅层，将中性物质和掺杂剂物质离子注入到非晶硅层中，以及在非晶硅层上形成上电极。

公开(公告)号：US5409848A

公开(公告)日：1995-04-25

申请号：US221740

申请日：1994-03-31

Applicant: Yu-Pin Han ,  Samuel J. S. Nagalingam

Inventor： Yu-Pin Han ,  Samuel J. S. Nagalingam

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10

CPC classification number: H01L29/66575 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  Y10S148/018

Abstract: The punchthrough capacity of a p-type semiconductor device is significantly improved by nonuniformly doping the p-channel with n-type implants such as phosphorus. The n-type dopants are implanted at large angles to form pocket implants within the channel region. The dose of the implants, angle of the implants and the thermal cycle annealing of the implants will be optimized for maximum punchthrough capability without substantially detracting from the performance of the semiconductor device.

Abstract translation: p型半导体器件的穿透能力通过使用n型植入物例如磷不均匀掺杂p沟道而显着提高。 n型掺杂剂以大角度注入以在沟道区内形成袋状植入物。 植入物的剂量，植入物的角度和植入物的热循环退火将针对最大穿透能力而优化，而不会显着降低半导体器件的性能。

公开(公告)号：USRE32800E

公开(公告)日：1988-12-13

申请号：US053269

申请日：1987-05-21

Applicant: Yu-Pin Han ,  Tsiu C. Chan

Inventor： Yu-Pin Han ,  Tsiu C. Chan

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/66598 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/78

Abstract: A short channel metal oxide semiconductor transistor device is processed without undesirable short channel effects, such as V.sub.T falloff and with a reasonable source-drain operating voltage support. In a substrate lightly doped with P-type conductivity material and source and drain region heavily doped with an N-type conductivity material, two lightly doped N- regions are disposed between the edge of the gate and the source and drain regions. A channel region is more heavily doped with P-type material than the substrate. Two regions extend from opposite sides of the channel region to an area generally below the two N- regions and above the substrate, which regions are more heavily doped than the channel regions.

公开(公告)号：US5801396A

公开(公告)日：1998-09-01

申请号：US488398

申请日：1995-06-07

Applicant: Tsiu Chiu Chan ,  Yu-Pin Han ,  Elmer H. Guritz ,  Richard A. Blanchard

Inventor： Tsiu Chiu Chan ,  Yu-Pin Han ,  Elmer H. Guritz ,  Richard A. Blanchard

IPC: H01L21/8244 ,  H01L27/06 ,  H01L27/092 ,  H01L27/11 ,  H01L29/04

CPC classification number: H01L27/11 ,  H01L27/0605 ,  H01L27/0922 ,  H01L27/1104 ,  H01L27/1108 ,  Y10S257/903 ,  Y10S438/981

Abstract: A CMOS device architecture which includes substrate-gated inverted PMOS transistors, as well as bulk NMOS. The inverted-PMOS channels are formed in a different layer from the NMOS gates, and these layers may even have different compositions. Moreover, the NMOS and inverted-PMOS devices have different gate oxide layers, so the thicknesses can be independently optimized. The drain underlap of the inverted device is defined by a patterning step, so it can be increased for high-voltage operation if desired.

公开(公告)号：US5793094A

公开(公告)日：1998-08-11

申请号：US579780

申请日：1995-12-28

Applicant: Ivan Sanchez ,  Yu-Pin Han ,  Ying-Tsong Loh ,  Walter D. Parmantie

Inventor： Ivan Sanchez ,  Yu-Pin Han ,  Ying-Tsong Loh ,  Walter D. Parmantie

IPC: H01L23/525 ,  H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002

Abstract: A method for substantially reducing variations in a programming voltage of an anti-fuse structure formed on an integrated circuit wafer. The anti-fuse structure has a metal-one layer, an anti-fuse layer disposed above the metal-one layer, a oxide layer disposed above the anti-fuse layer, and a via hole in the oxide layer through to the anti-fuse layer for receiving a deposition of a metal-two material. The method includes the step of rendering a selected anti-fuse area susceptible to fuse link formation by reducing a resistivity of the selected anti-fuse area to diffusion of atoms from one of the metal-one layer and the metal-two layer when a programming voltage is applied between the metal one layer and the metal two layer. The selected anti-fuse area is located in the anti-fuse layer and substantially adjacent to and outside of an anti-fuse area directly below the via hole. The method further includes the step of depositing the metal-two material into the via hole.

Abstract translation: 一种用于基本上减少在集成电路晶片上形成的抗熔丝结构的编程电压的变化的方法。 反熔丝结构具有金属一层，设置在金属一层上方的抗熔丝层，设置在抗熔融层上方的氧化物层，以及氧化物层中的通孔到反熔丝 用于接收金属二材料的沉积的层。 该方法包括以下步骤：当编程时，通过降低所选择的反熔丝区域与金属层和金属二层中的一个的原子的扩散，使选择的抗熔丝区域易于熔融链接形成 在金属一层和金属两层之间施加电压。 所选择的反熔丝区域位于反熔丝层中，并且基本上邻近通孔正下方的反熔丝区域的外部。 该方法还包括将金属二材料沉积到通孔中的步骤。

公开(公告)号：US5135888A

公开(公告)日：1992-08-04

申请号：US531014

申请日：1990-05-31

Applicant: Tsiu C. Chan ,  Yu-Pin Han ,  Elmer H. Guritz

Inventor： Tsiu C. Chan ,  Yu-Pin Han ,  Elmer H. Guritz

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/092 ,  H01L27/11

CPC classification number: H01L27/11 ,  H01L27/0605 ,  H01L27/1104 ,  H01L27/1108 ,  H01L28/20 ,  H01L27/1112

Abstract: A CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the data storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active area in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon P-channel transistors for use in CMOS SPRAM cells.

Abstract translation: CMOS SRAM单元在作为数据存储节点的公共节点和电源之间具有多晶硅信号线。 在该多晶硅信号线内制造场效应器件。 场效应器件的沟道通过薄栅电介质与衬底中的有源区域分离，并且衬底内的有源区域用作场效应器件的控制栅极。 这种器件可用于提供用于CMOS SPRAM单元的多晶硅P沟道晶体管。

公开(公告)号：US4599118A

公开(公告)日：1986-07-08

申请号：US654281

申请日：1984-09-24

Applicant: Yu-Pin Han ,  Tsiu C. Chan

Inventor： Yu-Pin Han ,  Tsiu C. Chan

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/308

CPC classification number: H01L29/66598 ,  H01L21/265 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/7833 ,  Y10S148/082

Abstract: A short channel metal oxide semiconductor transistor device is processed without undesirable short channel effects, such as V.sub.T falloff and with a reasonable source-drain operating voltage support. In a substrate lightly doped with P-type conductivity material and source and drain region heavily doped with an N-type conductivity material, two lightly doped N- regions are disposed between the edge of the gate and the source and drain regions. A channel region is more heavily doped with P-type material than the substrate. Two regions extend from opposite sides of the channel region to an area generally below the two N- regions and above the substrate, which regions are more heavily doped than the channel regions.

Abstract translation: 处理短沟道金属氧化物半导体晶体管器件而没有不期望的短沟道效应，例如VT衰减和合理的源极 - 漏极工作电压支持。 在轻掺杂有P型导电材料的衬底和重掺杂有N型导电材料的源极和漏极区域中，在栅极的边缘与源极和漏极区域之间设置两个轻掺杂的N区。 与衬底相比，沟道区比P型材料更重掺杂。 两个区域从通道区域的相对侧延伸到通常低于两个N-区域并且在衬底上方的区域，这些区域比沟道区域更重掺杂。

公开(公告)号：US4407696A

公开(公告)日：1983-10-04

申请号：US453214

申请日：1982-12-27

Applicant: Yu-Pin Han ,  Bing C. Ma

Inventor： Yu-Pin Han ,  Bing C. Ma

IPC: H01L21/762 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06 ,  H01L21/306

CPC classification number: H01L21/76213 ,  Y10S438/966

Abstract: A method is disclosed for fabricating an isolation oxidation (44), also referred to as field oxide, to separate the active regions on the surface of an MOS integrated circuit. On the surface of a semiconductor substrate (24) there are fabricated in successive layers an oxide layer (26), a polysilicon layer (28) and a nitride layer (30). A patterned resist layer (32) is formed on the surface of the nitride layer (30). The nitride layer (30) is etched through an opening (34) in the resist layer (32), which is then removed. The isolation oxidation (44) is then grown through an opening (36) in the nitride layer (30). The isolation oxidation (44) comprises oxide derived from the oxide layer (26) and from oxide produced from the polysilicon layer (28) and the semiconductor substrate (24). Next, the nitride layer (30), the polysilicon layer (28) and the oxide layer (26) are etched. The resulting isolation oxidation (44) has a bird's-beak area (46) which is less than 50% of the width of a bird'-beak area (14) produced using conventional MOS manufacturing processes.

Abstract translation: 公开了用于制造隔离氧化（44）的方法，其也称为场氧化物，以分离MOS集成电路的表面上的有源区。 在半导体衬底（24）的表面上，连续地制造氧化物层（26），多晶硅层（28）和氮化物层（30）。 在氮化物层（30）的表面上形成图案化的抗蚀剂层（32）。 通过抗蚀剂层（32）中的开口（34）蚀刻氮化物层（30），然后将其除去。 隔离氧化（44）然后通过氮化物层（30）中的开口（36）生长。 隔离氧化（44）包括衍生自氧化物层（26）的氧化物和由多晶硅层（28）和半导体衬底（24）产生的氧化物。 接下来，蚀刻氮化物层（30），多晶硅层（28）和氧化物层（26）。 所产生的隔离氧化（44）具有小于使用常规MOS制造工艺制造的鸟嘴区域（14）的宽度的50％的鸟嘴区域（46）。