公开(公告)号：US4407696A

公开(公告)日：1983-10-04

申请号：US453214

申请日：1982-12-27

Applicant: Yu-Pin Han ,  Bing C. Ma

Inventor： Yu-Pin Han ,  Bing C. Ma

IPC: H01L21/762 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06 ,  H01L21/306

CPC classification number: H01L21/76213 ,  Y10S438/966

Abstract: A method is disclosed for fabricating an isolation oxidation (44), also referred to as field oxide, to separate the active regions on the surface of an MOS integrated circuit. On the surface of a semiconductor substrate (24) there are fabricated in successive layers an oxide layer (26), a polysilicon layer (28) and a nitride layer (30). A patterned resist layer (32) is formed on the surface of the nitride layer (30). The nitride layer (30) is etched through an opening (34) in the resist layer (32), which is then removed. The isolation oxidation (44) is then grown through an opening (36) in the nitride layer (30). The isolation oxidation (44) comprises oxide derived from the oxide layer (26) and from oxide produced from the polysilicon layer (28) and the semiconductor substrate (24). Next, the nitride layer (30), the polysilicon layer (28) and the oxide layer (26) are etched. The resulting isolation oxidation (44) has a bird's-beak area (46) which is less than 50% of the width of a bird'-beak area (14) produced using conventional MOS manufacturing processes.

Abstract translation: 公开了用于制造隔离氧化（44）的方法，其也称为场氧化物，以分离MOS集成电路的表面上的有源区。 在半导体衬底（24）的表面上，连续地制造氧化物层（26），多晶硅层（28）和氮化物层（30）。 在氮化物层（30）的表面上形成图案化的抗蚀剂层（32）。 通过抗蚀剂层（32）中的开口（34）蚀刻氮化物层（30），然后将其除去。 隔离氧化（44）然后通过氮化物层（30）中的开口（36）生长。 隔离氧化（44）包括衍生自氧化物层（26）的氧化物和由多晶硅层（28）和半导体衬底（24）产生的氧化物。 接下来，蚀刻氮化物层（30），多晶硅层（28）和氧化物层（26）。 所产生的隔离氧化（44）具有小于使用常规MOS制造工艺制造的鸟嘴区域（14）的宽度的50％的鸟嘴区域（46）。

公开(公告)号：US6007641A

公开(公告)日：1999-12-28

申请号：US818228

申请日：1997-03-14

Applicant: Landon B. Vines ,  Felix H. Fujishiro ,  Yu-Pin Han

Inventor： Landon B. Vines ,  Felix H. Fujishiro ,  Yu-Pin Han

IPC: H01L21/28 ,  H01L21/306 ,  H01L21/316 ,  H01L29/51 ,  B08B3/00

CPC classification number: H01L21/28202 ,  H01L21/02063 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02307 ,  H01L21/31612 ,  H01L21/31662 ,  H01L29/518

Abstract: In the manufacture of an integrated circuit, contaminated oxide is replaced by relatively pure oxide using the following steps. First, a partially manufactured integrated circuit is bathed in an aqueous solution of hydrogen peroxide and ammonium hydroxide to oxidize organic materials and weaken bonds of metal contaminants to the integrated circuit substrate. Second, an aqueous rinse removes the oxidized organic materials and metal contaminants. Third, the integrated circuit is bathed in an aqueous solution of hydrogen fluoride and nitric acid. The hydrogen fluroide etches the contaminated oxide; the nitric acid combines with calcium and metal contaminants freed as the oxide is etched. The resulting nitride byproducts are highly soluble and easily removed in the following aqueous rinse. A drying step removes rinse water from the integrated circuit. Finally, an oxide formation step provides a relatively pure oxide layer. In the case of a gate oxide, the method removes a sacrificial oxide in preparation for gate oxide growth. In the case of formation of the submetal dielectric, oxide formation involves an TEOS oxide deposition. A key advantage of the invention is the improved calcium removal due to the nitric acid.

Abstract translation: 在集成电路的制造中，使用以下步骤用相对纯的氧化物代替污染的氧化物。 首先，将部分制造的集成电路沐浴在过氧化氢和氢氧化铵的水溶液中以氧化有机材料并减弱金属污染物与集成电路基板的接合。 第二，水性漂洗去除氧化的有机物质和金属污染物。 第三，将集成电路浸在氟化氢和硝酸的水溶液中。 氢氟酸蚀刻污染的氧化物; 硝酸与钙和金属污染物结合，氧化物被蚀刻掉。 所得的氮化物副产物是高度可溶的并且容易地在下列水性漂洗液中除去。 干燥步骤从集成电路中去除冲洗水。 最后，氧化物形成步骤提供相对纯的氧化物层。 在栅极氧化物的情况下，该方法除去用于栅极氧化物生长的牺牲氧化物。 在形成亚金属电介质的情况下，氧化物形成涉及TEOS氧化物沉积。 本发明的主要优点是由于硝酸而改善的钙去除。

公开(公告)号：US4868138A

公开(公告)日：1989-09-19

申请号：US172299

申请日：1988-03-23

Applicant: Tsiu C. Chan ,  Yu-Pin Han

Inventor： Tsiu C. Chan ,  Yu-Pin Han

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8244 ,  H01L27/092 ,  H01L27/11

CPC classification number: H01L21/76897 ,  H01L21/28518 ,  H01L21/76802 ,  H01L29/6659

Abstract: A process for forming electrical interconnect on MOS semiconductor integrated circuits includes the formation of a capping layer of oxide over the first level poly layer prior to patterning. The capping layer is then removed over selected regions. The conductive layer and capping oxide layer are then patterned to form transistor gates and interconnect. Source/drain regions are formed in active areas of the integrated circuit, and sidewall oxide is formed next to the patterned gate regions. When a second layer of interconnect is formed and patterned over the integrated circuit, contact between the first and second interconnect layers is made in the previously defined selected regions.

公开(公告)号：US06429144B1

公开(公告)日：2002-08-06

申请号：US09473451

申请日：1999-12-28

Applicant: Landon B. Vines ,  Felix H. Fujishiro ,  Yu-Pin Han

Inventor： Landon B. Vines ,  Felix H. Fujishiro ,  Yu-Pin Han

IPC: H01L21302

CPC classification number: H01L21/31111 ,  H01L21/0206 ,  H01L21/28211 ,  H01L21/28238

Abstract: In the manufacture of an integrated circuit, contaminated oxide is replaced by relatively pure oxide using the following steps. First, a partially manufactured integrated circuit is bathed in an aqueous solution of hydrogen peroxide and ammonium hydroxide to oxidize organic materials and weaken bonds of metal contaminants to the integrated circuit substrate. Second, an aqueous rinse removes the oxidized organic materials and metal contaminants. Third, the integrated circuit is bathed in an aqueous solution of hydrogen fluoride and nitric acid. The hydrogen fluroide etches the contaminated oxide; the nitric acid combines with calcium and metal contaminants freed as the oxide is etched. The resulting nitride byproducts are highly soluble and easily removed in the following aqueous rinse. A drying step removes rinse water from the integrated circuit. Finally, an oxide formation step provides a relatively pure oxide layer. In the case of a gate oxide, the method removes a sacrificial oxide in preparation for gate oxide growth. In the case of formation of the submetal dielectric, oxide formation involves an TEOS oxide deposition. A key advantage of the invention is the improved calcium removal due to the nitric acid.

Abstract translation: 在集成电路的制造中，使用以下步骤用相对纯的氧化物代替污染的氧化物。 首先，将部分制造的集成电路沐浴在过氧化氢和氢氧化铵的水溶液中以氧化有机材料并减弱金属污染物与集成电路基板的接合。 第二，水性漂洗去除氧化的有机物质和金属污染物。 第三，将集成电路浸在氟化氢和硝酸的水溶液中。 氢氟酸蚀刻污染的氧化物; 硝酸与钙和金属污染物结合，氧化物被蚀刻掉。 所得的氮化物副产物是高度可溶的并且容易地在下列水性漂洗液中除去。 干燥步骤从集成电路中去除冲洗水。 最后，氧化物形成步骤提供相对纯的氧化物层。 在栅极氧化物的情况下，该方法除去用于栅极氧化物生长的牺牲氧化物。 在形成亚金属电介质的情况下，氧化物形成涉及TEOS氧化物沉积。 本发明的主要优点是由于硝酸而改善的钙去除。

公开(公告)号：US5789795A

公开(公告)日：1998-08-04

申请号：US579824

申请日：1995-12-28

Applicant: Ivan Sanchez ,  Yu-Pin Han ,  Miguel A. Delgado ,  Ying-Tsong Loh

Inventor： Ivan Sanchez ,  Yu-Pin Han ,  Miguel A. Delgado ,  Ying-Tsong Loh

IPC: H01L23/525 ,  H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002

Abstract: An integrated circuit having a semiconductor substrate and an anti-fuse structure formed on the semiconductor substrate. The anti-fuse structure includes a metal-one layer and an anti-fuse layer disposed above the metal-one layer. The anti-fuse layer has a first resistance value when the anti-fuse structure is unprogrammed and a second resistance value lower than the first resistance value when the anti-fuse structure is programmed. There is further provided an etch stop layer disposed above the anti-fuse layer, and an inter-metal oxide layer disposed above the etch stop layer with the inter-metal oxide layer has a via formed therein. Additionally, there is further provided a metal-two layer disposed above the inter-metal oxide layer. In this structure, a portion of the metal-two layer is in electrical contact with the anti-fuse layer through the via in the inter-metal oxide layer.

Abstract translation: 具有形成在半导体衬底上的半导体衬底和抗熔丝结构的集成电路。 反熔丝结构包括金属一层和设置在金属一层上方的抗熔丝层。 当抗熔丝结构未被编程时，抗熔丝层具有第一电阻值，并且当编程防熔丝结构时，抗熔丝层具有低于第一电阻值的第二电阻值。 还提供了设置在反熔丝层上方的蚀刻停止层，并且设置在蚀刻停止层上方的金属间氧化物层与金属间氧化物层在其中形成通孔。 此外，还提供了设置在金属间氧化物层上方的金属二层。 在该结构中，金属二层的一部分通过金属间氧化物层中的通孔与抗熔融层电接触。

公开(公告)号：US5753540A

公开(公告)日：1998-05-19

申请号：US699867

申请日：1996-08-20

Applicant: Koucheng Wu ,  Ivan Sanchez ,  Yu-Pin Han ,  Ying-Tsong Loh

Inventor： Koucheng Wu ,  Ivan Sanchez ,  Yu-Pin Han ,  Ying-Tsong Loh

IPC: H01L23/525 ,  H01L21/82

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: Disclosed is a method for programming an antifuse structure. The antifuse structure is programmed by applying an alternating current having alternating current pulses between a bottom and a top electrode to generate a conduction path through an antifuse material sandwiched between the electrodes. The conduction path is formed incrementally due to an electron flow produced as a result of each alternating current pulse thereby defining the conduction path at a substantially centered portion of the antifuse material.

Abstract translation: 公开了一种用于编程反熔丝结构的方法。 反熔丝结构通过在底部和顶部电极之间施加具有交流电脉冲的交流电来编程，以产生穿过夹在电极之间的反熔丝的导电路径。 由于由于每个交流脉冲而产生的电子流，传导路径增量地形成，从而在反熔丝材料的基本中心部分处限定导电路径。

公开(公告)号：US5256895A

公开(公告)日：1993-10-26

申请号：US863519

申请日：1992-03-31

Applicant: Frank R. Bryant ,  Yu-Pin Han ,  Fu-Tai Liou

Inventor： Frank R. Bryant ,  Yu-Pin Han ,  Fu-Tai Liou

IPC: H01L21/32 ,  H01L21/762 ,  H01L27/12 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L21/32 ,  H01L21/76205

Abstract: Field oxide regions are formed between drive regions of a silicon substrate by forming over the substrate a sandwich of silicon dioxide, silicon nitride and silicon dioxide layers, opening the layers to expose a portion of the silicon substrate, removing a layer of the exposed substrate, forming side wall spacers on the edges of the opening, removing a layer of the silicon substrate exposed between the side wall spacers, and then reaching the exposed substrate for the thermal oxidation of the exposed substrate for forming the field oxide region. In those structures in which the field oxide is buried in the substrate as shown in FIG. 12, it may be feasible to use thicker field oxide regions and thereby to reduce the need for the heavily doped surface layer under the field oxide.

Abstract translation: 通过在衬底上形成二氧化硅，氮化硅和二氧化硅层的夹层来形成在硅衬底的驱动区之间的场氧化物区域，打开这些层以暴露硅衬底的一部分，去除暴露的衬底的一层， 在开口的边缘上形成侧壁间隔物，去除暴露在侧壁间隔物之间​​的硅衬底层，然后到达暴露的衬底，用于暴露衬底的热氧化以形成场氧化物区域。 在如图1所示的那些场地氧化物埋在衬底中的那些结构中。 如图12所示，可以使用较厚的场氧化物区域，从而减少对场氧化物下的重掺杂表面层的需要。

公开(公告)号：US5821136A

公开(公告)日：1998-10-13

申请号：US698129

申请日：1996-08-15

Applicant: Tsiu Chiu Chan ,  Yu-Pin Han ,  Elmer H. Guritz ,  Richard A. Blanchard

Inventor： Tsiu Chiu Chan ,  Yu-Pin Han ,  Elmer H. Guritz ,  Richard A. Blanchard

IPC: H01L21/8244 ,  H01L27/06 ,  H01L27/092 ,  H01L27/11 ,  H01L21/00 ,  H01L21/84

CPC classification number: H01L27/11 ,  H01L27/0605 ,  H01L27/0922 ,  H01L27/1104 ,  H01L27/1108 ,  Y10S257/903 ,  Y10S438/981

Abstract: A CMOS device architecture which includes substrate-gated inverted PMOS transistors, as well as bulk NMOS. The inverted-PMOS channels are formed in a different layer from the NMOS gates, and these layers may even have different compositions. Moreover, the NMOS and inverted-PMOS devices have different gate oxide layers, so the thicknesses can be independently optimized. The drain underlap of the inverted device is defined by a patterning step, so it can be increased for high-voltage operation if desired.

Abstract translation: 一种CMOS器件架构，包括基板门控反相PMOS晶体管，以及体NMOS。 反向PMOS沟道形成在与NMOS栅极不同的层中，并且这些层甚至可以具有不同的组成。 此外，NMOS和反向PMOS器件具有不同的栅极氧化物层，因此可以独立优化厚度。 倒置器件的漏极叠层由图案化步骤限定，因此如果需要，可以增加高压操作。

公开(公告)号：US5783467A

公开(公告)日：1998-07-21

申请号：US582844

申请日：1995-12-29

Applicant: Yu-Pin Han ,  Ying-Tsong Loh ,  Ivan Sanchez

Inventor： Yu-Pin Han ,  Ying-Tsong Loh ,  Ivan Sanchez

IPC: H01L21/8246 ,  H01L27/112 ,  H01L21/82

CPC classification number: H01L27/11206 ,  H01L27/112

Abstract: An antifuse structure includes a first electrode, a layer of enhanced amorphous silicon over the first electrode, and a second electrode over the layer of enhanced amorphous silicon. The layer of enhanced amorphous silicon is formed by an ion-implantation of a neutral species and a dopant species into a deposited layer of amorphous silicon, such that the antifuse structure will have a stable conductive link in a programmed state and such that it will be less susceptible to off-state leakage in an unprogrammed state. A method for making an antifuse structure includes forming a lower electrode, depositing an amorphous silicon layer over the lower electrode, ion-implanting a neutral species and a dopant species into the amorphous silicon layer, and forming an upper electrode over the amorphous silicon layer.

Abstract translation: 反熔丝结构包括第一电极，在第一电极上方的增强非晶硅层，以及增强非晶硅层上的第二电极。 通过将中性物质和掺杂剂物质的离子注入到非晶硅的沉积层中形成增强非晶硅层，使得反熔丝结构将在编程状态下具有稳定的导电链路，并且使得其将被 在非编程状态下较不易于断态泄漏。 制造反熔丝结构的方法包括形成下电极，在下电极上沉积非晶硅层，将中性物质和掺杂剂物质离子注入到非晶硅层中，以及在非晶硅层上形成上电极。

公开(公告)号：US5409848A

公开(公告)日：1995-04-25

申请号：US221740

申请日：1994-03-31

Applicant: Yu-Pin Han ,  Samuel J. S. Nagalingam

Inventor： Yu-Pin Han ,  Samuel J. S. Nagalingam

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10

CPC classification number: H01L29/66575 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  Y10S148/018

Abstract: The punchthrough capacity of a p-type semiconductor device is significantly improved by nonuniformly doping the p-channel with n-type implants such as phosphorus. The n-type dopants are implanted at large angles to form pocket implants within the channel region. The dose of the implants, angle of the implants and the thermal cycle annealing of the implants will be optimized for maximum punchthrough capability without substantially detracting from the performance of the semiconductor device.

Abstract translation: p型半导体器件的穿透能力通过使用n型植入物例如磷不均匀掺杂p沟道而显着提高。 n型掺杂剂以大角度注入以在沟道区内形成袋状植入物。 植入物的剂量，植入物的角度和植入物的热循环退火将针对最大穿透能力而优化，而不会显着降低半导体器件的性能。