公开(公告)号：US20200051868A1

公开(公告)日：2020-02-13

申请号：US16101963

申请日：2018-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Garo Jacques Derderian

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06

Abstract: Device structures and fabrication methods for a field-effect transistor. A semiconductor fin includes a first section and a second section in a lengthwise arrangement, a first gate structure overlapping the first section of the semiconductor fin, and a second gate structure overlapping the second section of the semiconductor fin. A pillar is arranged in the first section of the semiconductor fin. The pillar extends through a height of the semiconductor fin and across a width of the semiconductor fin.

公开(公告)号：US10475791B1

公开(公告)日：2019-11-12

申请号：US15994231

申请日：2018-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Garo Jacques Derderian ,  Laertis Economikos ,  Chun Yu Wong ,  Jiehui Shu ,  Shesh Mani Pandey

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234

Abstract: First and second fin-type field effect transistors (finFETs) are formed laterally adjacent one another extending from a top surface of an isolation layer. The first finFET has a first fin structure and the second finFET has a second fin structure. An insulator layer is on the first fin structure and the second fin structure. A gate conductor intersects the first fin structure and the second fin structure, and at least the insulator layer separates the gate conductor from the first fin structure and the second fin structure. Source and drain structures are on the first fin structure and the second fin structure laterally adjacent the gate conductor. The first fin structure has sidewalls that include a step and the second fin structure has sidewalls that do not include the step. The step is approximately parallel to the surface of the isolation layer.

公开(公告)号：US10418272B1

公开(公告)日：2019-09-17

申请号：US15976326

申请日：2018-05-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Garo Jacques Derderian ,  Hui Zang ,  John Zhang ,  Haigou Huang ,  Jinping Liu

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092

Abstract: At least one method, apparatus and system providing semiconductor devices with relatively short gate heights but without a relatively high risk of contact-to-gate shorts. In embodiments, the method, apparatus, and system may provide contact formation by way of self-aligned contact processes.

公开(公告)号：US20170069547A1

公开(公告)日：2017-03-09

申请号：US14845543

申请日：2015-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wen Pin Peng ,  Min-hwa Chi ,  Garo Jacques Derderian

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/823864 ,  H01L21/0206 ,  H01L21/02252 ,  H01L21/0234 ,  H01L21/31111 ,  H01L21/823814 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/78

Abstract: Disclosed herein is a method of forming a CMOS integrated circuit product (comprised of first and second opposite type transistors) that includes forming a first spacer proximate both the first and second gate structures, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, and forming first raised epi semiconductor material source/drain regions for the first transistor. Thereafter, performing a first surface oxidation process so as to selectively form a hydrophilic material on exposed surfaces of the first raised epi semiconductor material and performing an etching process on both the transistors so as to remove the initial second spacer and the layer of second spacer material.

Abstract translation: 本文公开了一种形成CMOS集成电路产品（由第一和第二相对型晶体管组成）的方法，其包括形成靠近第一和第二栅极结构的第一间隔物，形成靠近第一晶体管的第一间隔物的初始第二间隔物 以及在所述第二晶体管上方的第二间隔物层，以及为所述第一晶体管形成第一凸起的外延半导体材料源极/漏极区。 此后，进行第一表面氧化处理，以在第一隆起的外延半导体材料的暴露表面上选择性地形成亲水材料，并在两个晶体管上执行蚀刻处理，以去除初始的第二间隔物和第二间隔物材料层 。