公开(公告)号：US10559470B2

公开(公告)日：2020-02-11

申请号：US15876407

申请日：2018-01-22

申请人： GLOBALFOUNDRIES INC.

发明人： Haigou Huang ,  Jinsheng Gao ,  Hong Yu ,  Jinping Liu ,  Huang Liu

IPC分类号： H01L27/08 ,  H01L21/28 ,  H01L21/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/311 ,  H01L21/768

摘要： The present disclosure relates to semiconductor structures and, more particularly, to capping structures and methods of manufacture. The structure includes: a plurality of gate structures in a first location with a first density; a plurality of gate structures in a second location with a second density different than the first density; and a T-shaped capping structure protecting the plurality of gate structures in the first location and in the second location.

公开(公告)号：US20190393077A1

公开(公告)日：2019-12-26

申请号：US16016910

申请日：2018-06-25

申请人： GLOBALFOUNDRIES INC.

发明人： Chih-Chiang Chang ,  Haifeng` Sheng ,  Jiehui Shu ,  Haigou Huang ,  Pei Liu ,  Jinping Liu ,  Haiting Wang ,  Daniel J. Jaeger

IPC分类号： H01L21/762 ,  H01L29/66 ,  H01L21/768 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

摘要： The present disclosure relates to methods for forming fill materials in trenches having different widths and related structures. A method may include: forming a first fill material in a first and second trench where the second trench has a greater width than the first trench; removing a portion of the first fill material from each trench and forming a second fill material over the first fill material; removing a portion of the first and second fill material within the second trench; and forming a third fill material in the second trench. The structure may include a first fill material in trenches having different widths wherein the upper surfaces of the first fill material in each trench are substantially co-planar. The structure may also include a second fill material on the first fill material in each trench, the second fill material having a substantially equal thickness in each trench.

公开(公告)号：US20190355624A1

公开(公告)日：2019-11-21

申请号：US16529162

申请日：2019-08-01

申请人： GLOBALFOUNDRIES INC.

发明人： Asli Sirman ,  Jiehui Shu ,  Chih-Chiang Chang ,  Huy Cao ,  Haigou Huang ,  Jinping Liu

IPC分类号： H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/66

摘要： Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches.

公开(公告)号：US10483369B2

公开(公告)日：2019-11-19

申请号：US15797723

申请日：2017-10-30

申请人： GLOBALFOUNDRIES Inc.

发明人： Haigou Huang ,  Xusheng Wu ,  Jinsheng Gao

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/8238

摘要： One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, the sacrificial gate structure comprising a sacrificial gate insulation layer and a multi-layer sacrificial gate electrode structure, removing the sacrificial gate structure to form a replacement gate cavity, and forming a replacement gate structure in the replacement gate cavity.

公开(公告)号：US20190341475A1

公开(公告)日：2019-11-07

申请号：US15970217

申请日：2018-05-03

申请人： GLOBALFOUNDRIES INC.

发明人： Jiehui Shu ,  Laertis Economikos ,  Xusheng Wu ,  John Zhang ,  Haigou Huang ,  Hui Zhan ,  Tao Han ,  Haiting Wang ,  Jinping Liu ,  Hui Zang

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238

摘要： In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.

公开(公告)号：US20190304843A1

公开(公告)日：2019-10-03

申请号：US15936734

申请日：2018-03-27

申请人： GLOBALFOUNDRIES INC.

发明人： Asli Sirman ,  Jiehui Shu ,  Chih-Chiang Chang ,  Huy Cao ,  Haigou Huang ,  Jinping Liu

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L29/66

摘要： Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches.

公开(公告)号：US10347729B2

公开(公告)日：2019-07-09

申请号：US15590459

申请日：2017-05-09

申请人： GLOBALFOUNDRIES Inc.

发明人： Xusheng Wu ,  Haigou Huang

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40

摘要： Devices and methods of fabricating integrated circuit devices for increasing performance through gate cut last processes are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a plurality of fins, an STI layer, an oxide layer, and a gate material over the oxide layer, the fins extending into the gate material; removing the gate material and the oxide layer; depositing a high k material on a top surface of the STI layer, surrounding the fins; depositing a gate stack over the high k material; filling the top of the device with a gate contact metal; etching a portion of the gate contact metal, the metal gate stack, and the high k material; and filling the portion with an inter-layer dielectric. Also disclosed is an intermediate device formed by the method.

公开(公告)号：US20190035739A1

公开(公告)日：2019-01-31

申请号：US15661029

申请日：2017-07-27

申请人： GLOBALFOUNDRIES INC.

发明人： Qiang Fang ,  Haigou Huang ,  Shafaat Ahmed ,  Changhong Wu ,  Dinesh R. Koli

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L21/288 ,  H01L21/285 ,  H01L21/3213

摘要： The disclosure relates to a method of forming a Co contact module, the method including depositing a liner layer on a trench block, partially plating the lined trenches with Co as a first metal such that the resulting Co layer has a top surface below an opening top surface of a shallowest trench, depositing a second metal on the Co layer and exposed surfaces of the liner layer, planarizing the second metal layer, and etching the second metal layer and portions of the liner layer. The disclosure also relates to a Co contact module formed by the noted method.

公开(公告)号：US20190027586A1

公开(公告)日：2019-01-24

申请号：US15654165

申请日：2017-07-19

申请人： GLOBALFOUNDRIES Inc.

发明人： Hui Zang ,  Haigou Huang

IPC分类号： H01L29/66 ,  H01L29/78

摘要： Structures for a vertical-transport field-effect transistor and methods for forming a structure for a vertical-transport field-effect transistor. A semiconductor fin is formed on a source/drain region. A gate stack is deposited that coats the semiconductor fin and a contact landing area of the source/drain region adjacent to the semiconductor fin. The gate stack is patterned to remove the gate stack from the contact landing area and to form a gate electrode having a section adjacent to the contact landing area. The section of the gate electrode is laterally recessed to form a cavity, and a dielectric spacer is formed in the cavity.

公开(公告)号：US10176995B1

公开(公告)日：2019-01-08

申请号：US15673232

申请日：2017-08-09

申请人： GLOBALFOUNDRIES INC.

发明人： Xusheng Wu ,  Haigou Huang

IPC分类号： H01L21/8238 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/768 ,  H01L21/84 ,  H01L21/28 ,  H01L29/66

摘要： At least one method, apparatus and system disclosed herein involves a gate cut process using a stress material for a finFET device. A set of fins are formed on a semiconductor substrate. A gate region is formed above a portion of the set of fins. A gate cut trench is formed within the gate region. A dielectric material comprising an intrinsic stress is deposited into the gate cut region. A replacement metal gate process is performed in the gate region. Residue metal features are removed about the gate cut region.