公开(公告)号：US10439026B2

公开(公告)日：2019-10-08

申请号：US15786284

申请日：2017-10-17

申请人： GLOBALFOUNDRIES INC.

发明人： Chun Yu Wong ,  Hui Zang ,  Xusheng Wu

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/161

摘要： The present disclosure relates to semiconductor structures and, more particularly, to fin structures with single diffusion break facet improvement using an epitaxial insulator and methods of manufacture. The structure includes: a plurality of fin structures; an insulator material filling a cut between adjacent fin structures of the plurality of fin structures; a metal material (e.g., rare earth oxide or SrTiO3) at least partially lining the cut; and an epitaxial source region or epitaxial drain region in at least one of the plurality of fin structures and adjacent to the metal material.

公开(公告)号：US09245790B2

公开(公告)日：2016-01-26

申请号：US13747579

申请日：2013-01-23

申请人： GLOBALFOUNDRIES, Inc.

发明人： Sarasvathi Thangaraju ,  Chun Yu Wong

IPC分类号： H01L29/40 ,  H01L21/768 ,  H01L23/528

CPC分类号： H01L21/76807 ,  H01L21/76898 ,  H01L23/528 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuits, methods of forming integrated circuits, and methods of sensing voiding between a through-semiconductor via and a subsequent layer that overlies the through-semiconductor via in integrated circuits are provided. An exemplary method of forming an integrated circuit includes forming a plurality of semiconductor devices on a semiconductor substrate. A through-semiconductor via is formed in the semiconductor substrate, and an interlayer dielectric layer is formed that overlies the through-semiconductor via and the plurality of semiconductor devices. A first interconnect via is embedded within the interlayer dielectric layer, and a second interconnect via is embedded within the interlayer dielectric layer. The first interconnect via and the second interconnect via are in electrical communication with the through-semiconductor via at spaced locations from each other on the through-semiconductor via.

摘要翻译： 提供集成电路，形成集成电路的方法以及在集成电路中覆盖贯穿半导体通孔的贯穿半导体通孔和后续层之间感应空隙的方法。 形成集成电路的示例性方法包括在半导体衬底上形成多个半导体器件。 在半导体衬底中形成贯通半导体通孔，并且形成覆盖贯通半导体通孔和多个半导体器件的层间电介质层。 第一互连通孔嵌入在层间电介质层内，并且第二互连通孔嵌入在层间电介质层内。 第一互连通孔和第二互连通孔在穿通半导体通孔上与穿通半导体通孔彼此间隔开的位置电连通。

公开(公告)号：US10804199B2

公开(公告)日：2020-10-13

申请号：US16140545

申请日：2018-09-25

申请人： GLOBALFOUNDRIES INC.

发明人： Yongjun Shi ,  Ruilong Xie ,  Nan Fu ,  Chun Yu Wong

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L21/027 ,  H01L23/532 ,  H01L21/285 ,  H01L23/522 ,  H01L21/321 ,  H01L21/3105

摘要： A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer with a plurality of first conductive lines formed of a first conductive material in a dielectric layer. At least one via opening is formed over the plurality of first conductive lines and an interconnect via formed of a second conductive material is formed in the via opening, wherein the formed interconnect via has a convex top surface.

公开(公告)号：US10468481B2

公开(公告)日：2019-11-05

申请号：US15875132

申请日：2018-01-19

申请人： GLOBALFOUNDRIES INC.

发明人： Haiting Wang ,  Hui Zang ,  Chun Yu Wong ,  Kwan-Yong Lim

IPC分类号： H01L29/06 ,  H01L21/762 ,  H01L27/088

摘要： A methodology for forming a single diffusion break structure in a FinFET device involves localized, in situ oxidation of a portion of a semiconductor fin. Fin oxidation within a fin cut region may be preceded by the formation of epitaxial source/drain regions over the fin, as well as by a gate cut module, where portions of a sacrificial gate that straddle the fin are replaced by an isolation layer. Localized oxidation of the fin enables the stress state in adjacent, un-oxidized portions of the fin to be retained, which may beneficially impact carrier mobility and hence conductivity within channel portions of the fin.

公开(公告)号：US10910276B1

公开(公告)日：2021-02-02

申请号：US16589789

申请日：2019-10-01

申请人： GLOBALFOUNDRIES INC.

发明人： Yongjun Shi ,  Xinyuan Dou ,  Chun Yu Wong ,  Hongliang Shen ,  Baofu Zhu

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L21/762 ,  H01L27/092 ,  H01L29/78

摘要： A structure, an STI structure and a related method are disclosed. The structure may include an active region extending from a substrate; a gate extending over the active region; and a source/drain region in the active region, and an STI structure. The STI structure includes a liner and a fill layer on the liner along the opposed longitudinal sides of a lower portion of the active region, and the fill layer along the opposed ends of the active region. The liner may include a tensile stress-inducing liner that imparts a transverse-to-length tensile stress in at least a lower portion of the active region but not lengthwise. The liner can be applied in an n-FET region and/or a p-FET region to improve performance.

公开(公告)号：US10475791B1

公开(公告)日：2019-11-12

申请号：US15994231

申请日：2018-05-31

申请人： GLOBALFOUNDRIES INC.

发明人： Hui Zang ,  Garo Jacques Derderian ,  Laertis Economikos ,  Chun Yu Wong ,  Jiehui Shu ,  Shesh Mani Pandey

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L21/8234

摘要： First and second fin-type field effect transistors (finFETs) are formed laterally adjacent one another extending from a top surface of an isolation layer. The first finFET has a first fin structure and the second finFET has a second fin structure. An insulator layer is on the first fin structure and the second fin structure. A gate conductor intersects the first fin structure and the second fin structure, and at least the insulator layer separates the gate conductor from the first fin structure and the second fin structure. Source and drain structures are on the first fin structure and the second fin structure laterally adjacent the gate conductor. The first fin structure has sidewalls that include a step and the second fin structure has sidewalls that do not include the step. The step is approximately parallel to the surface of the isolation layer.

公开(公告)号：US10043764B2

公开(公告)日：2018-08-07

申请号：US15247513

申请日：2016-08-25

申请人： GLOBALFOUNDRIES INC.

发明人： Huang Liu ,  Sarasvathi Thangaraju ,  Chun Yu Wong

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498 ,  H01L25/07

摘要： Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress, thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

公开(公告)号：US09601428B2

公开(公告)日：2017-03-21

申请号：US14865589

申请日：2015-09-25

申请人： GLOBALFOUNDRIES Inc.

发明人： Chun Yu Wong ,  Jagar Singh ,  Ashish Baraskar ,  Min-hwa Chi

IPC分类号： H01L23/525 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/283 ,  H01L29/06 ,  H01L27/112

CPC分类号： H01L23/5256 ,  H01L21/0226 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/283 ,  H01L21/3205 ,  H01L27/11206 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785

摘要： Semiconductor fuses with nanowire fuse links and fabrication methods thereof are presented. The methods include, for instance: fabricating a semiconductor fuse, the semiconductor fuse including at least one nanowire fuse link, and the fabricating including: forming at least one nanowire, the at least one nanowire including a semiconductor material; and reacting the at least one nanowire with a metal to form the at least one nanowire fuse link of the semiconductor fuse, the at least one nanowire fuse link including a semiconductor-metal alloy. In another aspect, a structure is presented. The structure includes: a semiconductor fuse, the semiconductor fuse including: at least one nanowire fuse link, the at least one nanowire fuse link including a semiconductor-metal alloy.

公开(公告)号：US09455188B2

公开(公告)日：2016-09-27

申请号：US13744551

申请日：2013-01-18

申请人： GLOBALFOUNDRIES Inc.

发明人： Huang Liu ,  Sarasvathi Thangaraju ,  Chun Yu Wong

IPC分类号： H01L23/48 ,  H01L21/336 ,  H01L21/768

CPC分类号： H01L23/562 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49894 ,  H01L25/072 ,  H01L2924/0002 ,  H01L2924/00

摘要： Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress, thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

摘要翻译： 本发明的方面通常涉及用于形成半导体器件的方法，例如在TSV和晶体管之间具有“缓冲区”或间隙层的TSV器件。 间隙层通常填充有低应力的薄膜填充材料，其控制装置上的应力和裂纹形成。 此外，间隙层确保TSV和晶体管之间的一定空间距离，以减少温度偏移的不利影响。

公开(公告)号：US10461029B2

公开(公告)日：2019-10-29

申请号：US15686230

申请日：2017-08-25

申请人： GLOBALFOUNDRIES INC.

发明人： Chun Yu Wong ,  Jagar Singh

IPC分类号： H01L23/525 ,  H01L23/528 ,  H01L21/762 ,  H01L29/161

摘要： Methods of forming a hybrid electrically programmable fuse (e-fuse) structure and the hybrid e-fuse structure are disclosed. In various embodiments, the e-fuse structure includes: a substrate; an insulator layer over the substrate; a pair of contact regions overlying the insulator layer; and a silicide channel overlying the insulator layer and connecting the pair of contact regions, the silicide channel having a first portion including silicide silicon and a second portion coupled with the first portion and on a common level with the first portion, the second portion including silicide silicon germanium (SiGe) or silicide silicon phosphorous (SiP).