公开(公告)号：US09275896B2

公开(公告)日：2016-03-01

申请号：US14341985

申请日：2014-07-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Deniz Elizabeth Civay ,  Ji Xu ,  Gerard Schmid ,  Guillaume Bouche ,  Richard A. Farrell

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L21/76802 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76897

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a graphoepitaxy DSA directing confinement well using a sidewall of an etch layer that overlies a semiconductor substrate. The graphoepitaxy DSA directing confinement well is filled with a block copolymer. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etchable phase is etched while leaving the etch resistant phase substantially in place to define an etch mask with a nanopattern. The nanopattern is transferred to the etch layer.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括使用覆盖在半导体衬底上的蚀刻层的侧壁来形成引导限制阱的图形外延生成DSA。 使用嵌段共聚物填充指向封闭的石墨电极DSA。 嵌段共聚物被相分离成可蚀刻相和耐蚀刻相。 蚀刻相位被蚀刻，同时使耐腐蚀相位基本上到位以限定具有纳米图案的蚀刻掩模。 将纳米图案转移到蚀刻层。