公开(公告)号：US10685847B2

公开(公告)日：2020-06-16

申请号：US15598905

申请日：2017-05-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Richard A. Farrell ,  Gerard Schmid ,  Ajey Poovannummoottil Jacob

IPC: H01L21/31 ,  H01L21/311 ,  H01L29/78 ,  H01L29/06 ,  H01L21/308 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L21/8234

Abstract: One illustrative device includes, among other things, at least one fin defined in a semiconductor substrate and a substantially vertical nanowire having an oval-shaped cross-section disposed on a top surface of the at least one fin.

公开(公告)号：US10186577B2

公开(公告)日：2019-01-22

申请号：US14477096

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Richard A. Farrell ,  Gerard Schmid ,  Ajey Poovannummoottil Jacob

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/308 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L21/311

Abstract: A method includes forming a first directed self-assembly material above a substrate. The substrate is patterned using the first directed self-assembly material to define at least one fin in the semiconductor substrate. A second directed self-assembly material is formed above the at least one fin to expose a top surface of the at least one fin. A substantially vertical nanowire is formed on the top surface of the at least one fin. At least a first dimension of the vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material and a second dimension of the vertical nanowire is defined by an intrinsic pitch of the second directed self-assembly material.

公开(公告)号：US09865682B2

公开(公告)日：2018-01-09

申请号：US14476918

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Richard A. Farrell ,  Gerard Schmid ,  Ajey Poovannummoottil Jacob

IPC: H01L29/06 ,  H01L29/78 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3086 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7854

Abstract: A method includes forming at least one fin on a semiconductor substrate. A nanowire material is formed above the fin. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the nanowire material. The nanowire material is etched using the hard mask layer as an etch mask to define a substantially vertical nanowire on a top surface of the at least one fin, wherein at least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.

公开(公告)号：US20170263465A1

公开(公告)日：2017-09-14

申请号：US15598905

申请日：2017-05-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Richard A. Farrell ,  Gerard Schmid ,  Ajey Poovannummoottil Jacob

IPC: H01L21/311 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/308 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L21/31144 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3086 ,  H01L21/823487 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7854 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696

Abstract: One illustrative device includes, among other things, at least one fin defined in a semiconductor substrate and a substantially vertical nanowire having an oval-shaped cross-section disposed on a top surface of the at least one fin.

公开(公告)号：US09698025B2

公开(公告)日：2017-07-04

申请号：US14476879

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Richard A. Farrell ,  Gerard Schmid ,  Ajey Poovannummoottil Jacob

IPC: H01L21/311 ,  H01L29/78 ,  H01L29/06 ,  H01L21/308 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L21/8234

CPC classification number: H01L21/31144 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3086 ,  H01L21/823487 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7854

Abstract: A method includes forming at least one fin on a semiconductor substrate. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the top surface of the fin. A substantially vertical nanowire is formed on the exposed top surface. At least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.

公开(公告)号：US09613807B2

公开(公告)日：2017-04-04

申请号：US14692359

申请日：2015-04-21

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ji Xu ,  Gerard Schmid ,  Richard A. Farrell

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/0274

Abstract: Methods for directed self-assembly (DSA) using chemoepitaxy in the design and fabrication of integrated circuits are disclosed herein. An exemplary method includes forming an A or B-block attracting layer over a base semiconductor layer, forming a trench in the A or B-block attracting layer to expose a portion of the base semiconductor layer, and forming a neutral brush or mat or SAMs layer coating within the trench and over the base semiconductor layer. The method further includes forming a block copolymer layer over the neutral layer coating and over the A or B-block attracting layer and annealing the block copolymer layer to form a plurality of vertically-oriented, cylindrical structures within the block copolymer layer.

公开(公告)号：US20160071930A1

公开(公告)日：2016-03-10

申请号：US14477096

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Richard A. Farrell ,  Gerard Schmid ,  Ajey Poovannummoottil Jacob

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3086 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7854

Abstract: A method includes forming a first directed self-assembly material above a substrate. The substrate is patterned using the first directed self-assembly material to define at least one fin in the semiconductor substrate. A second directed self-assembly material is formed above the at least one fin to expose a top surface of the at least one fin. A substantially vertical nanowire is formed on the top surface of the at least one fin. At least a first dimension of the vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material and a second dimension of the vertical nanowire is defined by an intrinsic pitch of the second directed self-assembly material.

Abstract translation: 一种方法包括在基底上形成第一定向自组装材料。 使用第一定向自组装材料对衬底进行构图，以限定半导体衬底中的至少一个鳍。 第二定向自组装材料形成在至少一个翅片上方以暴露至少一个翅片的顶表面。 在至少一个翅片的顶表面上形成基本垂直的纳米线。 垂直纳米线的至少第一尺寸由第一定向自组装材料的固有间距限定，并且垂直纳米线的第二尺寸由第二定向自组装材料的固有间距限定。

公开(公告)号：US20160071845A1

公开(公告)日：2016-03-10

申请号：US14476879

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Richard A. Farrell ,  Gerard Schmid ,  Ajey Poovannummoottil Jacob

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/311 ,  H01L21/308 ,  H01L21/306 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L21/31144 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3086 ,  H01L21/823487 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7854

Abstract: A method includes forming at least one fin on a semiconductor substrate. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the top surface of the fin. A substantially vertical nanowire is formed on the exposed top surface. At least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.

Abstract translation: 一种方法包括在半导体衬底上形成至少一个翅片。 在翅片上形成硬掩模层。 第一定向自组装材料形成在硬掩模层之上。 使用第一定向自组装材料的一部分作为蚀刻掩模对硬掩模层进行图案化，以暴露鳍的顶表面的一部分。 在暴露的顶表面上形成基本垂直的纳米线。 基本垂直的纳米线的至少一个维度由第一定向自组装材料的固有间距限定。

公开(公告)号：US20160035565A1

公开(公告)日：2016-02-04

申请号：US14692359

申请日：2015-04-21

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Ji Xu ,  Gerard Schmid ,  Richard A. Farrell

IPC: H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/0274

Abstract: Methods for directed self-assembly (DSA) using chemoepitaxy in the design and fabrication of integrated circuits are disclosed herein. An exemplary method includes forming an A or B-block attracting layer over a base semiconductor layer, forming a trench in the A or B-block attracting layer to expose a portion of the base semiconductor layer, and forming a neutral brush or mat or SAMs layer coating within the trench and over the base semiconductor layer. The method further includes forming a block copolymer layer over the neutral layer coating and over the A or B-block attracting layer and annealing the block copolymer layer to form a plurality of vertically-oriented, cylindrical structures within the block copolymer layer.

Abstract translation: 本文公开了在集成电路的设计和制造中使用化学外延的定向自组装（DSA）的方法。 一种示例性方法包括在基底半导体层上形成A或B块吸引层，在A或B块吸引层中形成沟槽以暴露基底半导体层的一部分，以及形成中性刷或垫或SAM 在该沟槽内和该基底半导体层上方涂层。 该方法还包括在中性层涂层上和在A或B嵌段吸引层之上形成嵌段共聚物层，并使嵌段共聚物层退火以在嵌段共聚物层内形成多个垂直取向的圆柱形结构。

公开(公告)号：US20150303055A1

公开(公告)日：2015-10-22

申请号：US14254460

申请日：2014-04-16

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ji Xu ,  Gerard Schmid ,  Richard A. Farrell

IPC: H01L21/027 ,  H01L21/02

CPC classification number: H01L21/0276 ,  H01L21/0272 ,  H01L21/0273 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31058

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes surface treating exposed portions of an anti-reflective coating (ARC) that overlie a semiconductor substrate to form surface treated ARC portions. A neutral layer is formed overlying the anti-reflective coating including over the surface treated ARC portions. First portions of the neutral layer are selectively removed and second portions of the anti-reflective coating that are disposed under the first portions laterally adjacent to the surface treated ARC portions are exposed to define a guide pattern. A block copolymer layer is deposited overlying the guide pattern. The block copolymer layer is phase separated to define a nanopattern that is registered to the guide pattern.

Abstract translation: 提供了制造集成电路的方法。 在一个实例中，用于制造集成电路的方法包括：表面处理覆盖在半导体衬底上以形成经表面处理的ARC部分的抗反射涂层（ARC）的暴露部分。 形成覆盖在抗反射涂层上的中性层，包括在经表面处理的ARC部分上。 中性层的第一部分被选择性地去除，并且设置在与表面处理的ARC部分横向相邻的第一部分下面的抗反射涂层的第二部分被暴露以限定引导图案。 沉积在引导图案上的嵌段共聚物层。 嵌段共聚物层被相分离以限定与导向图案对应的纳米图案。