公开(公告)号：US20140178824A1

公开(公告)日：2014-06-26

申请号：US13726732

申请日：2012-12-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Moshe E Preil ,  Gerard M. Schmid ,  Richard A. Farrell ,  Ji Xu ,  Thomas I. Wallow

IPC: G03F7/20

CPC classification number: G03F7/0002

Abstract: Approaches for utilizing laser annealing to optimize lithographic processes such as directed self assembly (DSA) are provided. Under a typical approach, a substrate (e.g., a wafer) will be subjected to a lithographic process (e.g., having a set of stages/phases, aspects, etc.) such as DSA. Before or during such process, a set of laser annealing passes/scans will be made over the substrate to optimize one or more of the stages. In addition, the substrate could be subjected to additional processes such as hotplate annealing, etc. Still yet, in making a series of laser annealing passes, the techniques utilized and/or beam characteristics of each pass could be varied to further optimize the results.

Abstract translation: 提供了利用激光退火优化光刻工艺的方法，如定向自组装（DSA）。 在典型的方法下，衬底（例如，晶片）将经历诸如DSA的光刻工艺（例如，具有一组阶段/阶段，方面等）。 在此过程之前或期间，将在衬底上进行一组激光退火通过/扫描以优化一个或多个阶段。 此外，可以对基板进行额外的加工，例如热板退火等。然而，在进行一系列激光退火过程中，可以改变所使用的技术和/或每个通过的光束特性以进一步优化结果。

公开(公告)号：US09305834B1

公开(公告)日：2016-04-05

申请号：US14586268

申请日：2014-12-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Azat Latypov ,  Ji Xu

IPC: G06F17/50 ,  H01L21/768

CPC classification number: H01L21/76816 ,  G03F7/0002 ,  H01L21/31144

Abstract: Methods for fabricating integrated circuits using directed self-assembly to form via and contact holes are disclosed. An exemplary method includes determining a natural, hexagonal separation distance L0 between cylinders formed in a block copolymer (BCP) material during directed self-assembly (DSA) and determining an integrated circuit feature pitch PA according to the following formula: PA=L0*(sqrt(3)/2)*n, wherein n is a positive integer. The method further includes generating an integrated circuit layout design better accommodating the natural formation arrangement of polymeric cylinders, wherein integrated circuit features are spaced in accordance with the integrated circuit feature pitch PA and wherein via or contact structures are physically and electrically connected to the integrated circuit features and fabricating the integrated circuit features and the via or contact structures on a semiconductor work-in-process (WIP) in accordance with the integrated circuit layout design, wherein the via or contact structures are fabricated utilizing DSA with BCP material.

Abstract translation: 公开了使用定向自组装形成通孔和接触孔的集成电路的制造方法。 示例性方法包括在定向自组装（DSA）期间确定在嵌段共聚物（BCP）材料中形成的气缸之间的天然六边形间隔距离L0，并根据以下公式确定集成电路特征间距PA：PA = L0 *（ sqrt（3）/ 2）* n，其中n是正整数。 该方法还包括生成更好地适应聚合物气瓶的自然形成布置的集成电路布局设计，其中集成电路特征根据集成电路特征间距PA间隔开，并且其中通孔或接触结构物理和电连接到集成电路 特征和制造集成电路特征以及根据集成电路布局设计的半导体工艺（WIP）上的通孔或接触结构，其中通过或接触结构使用具有BCP材料的DSA制造。

公开(公告)号：US20160035565A1

公开(公告)日：2016-02-04

申请号：US14692359

申请日：2015-04-21

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Ji Xu ,  Gerard Schmid ,  Richard A. Farrell

IPC: H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/0274

Abstract: Methods for directed self-assembly (DSA) using chemoepitaxy in the design and fabrication of integrated circuits are disclosed herein. An exemplary method includes forming an A or B-block attracting layer over a base semiconductor layer, forming a trench in the A or B-block attracting layer to expose a portion of the base semiconductor layer, and forming a neutral brush or mat or SAMs layer coating within the trench and over the base semiconductor layer. The method further includes forming a block copolymer layer over the neutral layer coating and over the A or B-block attracting layer and annealing the block copolymer layer to form a plurality of vertically-oriented, cylindrical structures within the block copolymer layer.

Abstract translation: 本文公开了在集成电路的设计和制造中使用化学外延的定向自组装（DSA）的方法。 一种示例性方法包括在基底半导体层上形成A或B块吸引层，在A或B块吸引层中形成沟槽以暴露基底半导体层的一部分，以及形成中性刷或垫或SAM 在该沟槽内和该基底半导体层上方涂层。 该方法还包括在中性层涂层上和在A或B嵌段吸引层之上形成嵌段共聚物层，并使嵌段共聚物层退火以在嵌段共聚物层内形成多个垂直取向的圆柱形结构。

公开(公告)号：US20150303055A1

公开(公告)日：2015-10-22

申请号：US14254460

申请日：2014-04-16

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ji Xu ,  Gerard Schmid ,  Richard A. Farrell

IPC: H01L21/027 ,  H01L21/02

CPC classification number: H01L21/0276 ,  H01L21/0272 ,  H01L21/0273 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31058

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes surface treating exposed portions of an anti-reflective coating (ARC) that overlie a semiconductor substrate to form surface treated ARC portions. A neutral layer is formed overlying the anti-reflective coating including over the surface treated ARC portions. First portions of the neutral layer are selectively removed and second portions of the anti-reflective coating that are disposed under the first portions laterally adjacent to the surface treated ARC portions are exposed to define a guide pattern. A block copolymer layer is deposited overlying the guide pattern. The block copolymer layer is phase separated to define a nanopattern that is registered to the guide pattern.

Abstract translation: 提供了制造集成电路的方法。 在一个实例中，用于制造集成电路的方法包括：表面处理覆盖在半导体衬底上以形成经表面处理的ARC部分的抗反射涂层（ARC）的暴露部分。 形成覆盖在抗反射涂层上的中性层，包括在经表面处理的ARC部分上。 中性层的第一部分被选择性地去除，并且设置在与表面处理的ARC部分横向相邻的第一部分下面的抗反射涂层的第二部分被暴露以限定引导图案。 沉积在引导图案上的嵌段共聚物层。 嵌段共聚物层被相分离以限定与导向图案对应的纳米图案。