公开(公告)号：US08906768B2

公开(公告)日：2014-12-09

申请号：US13840692

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Hoong Shing Wong ,  Min-hwa Chi

IPC: H01L29/775 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/7848

Abstract: For the formation of a stressor on one or more of a source and drain defined on a fin of FINFET semiconductor structure, a method can be employed including performing selective epitaxial growth (SEG) on one or more of the source and drain defined on the fin, separating the fin from a bulk silicon substrate at one or more of the source and drain, and further performing SEG on one or more of the source and drain to form a wrap around epitaxial growth stressor that stresses a channel connecting the source and drain. The formed stressor can be formed so that the epitaxial growth material defining a wrap around configuration connects to the bulk substrate. The formed stressor can increase mobility in a channel connecting the defined source and drain.

Abstract translation: 为了在限定在FINFET半导体结构的鳍上的一个或多个源极和漏极上形成应力源，可以采用一种方法，包括在鳍上限定的一个或多个源极和漏极上执行选择性外延生长（SEG） 在源极和漏极中的一个或多个处将散热片与体硅衬底分离开，并且在源极和漏极之一上进一步执行SEG，以形成围绕外延生长应力的环绕，该外延生长应力应力连接源极和漏极的沟道。 形成的应力器可以形成为使得限定缠绕结构的外延生长材料连接到本体基板。 所形成的应力源可以增加连接限定的源极和漏极的通道中的迁移率。

公开(公告)号：US09147680B2

公开(公告)日：2015-09-29

申请号：US13943944

申请日：2013-07-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Kristina Trevino ,  Yuan-Hung Lin ,  Gabriel Padron Wells ,  Chang Ho Maeng ,  Taejoon Han ,  Hoong Shing Wong

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L27/088 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

Abstract: Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating such integrated circuits are provided. A method includes providing a dielectric layer overlying a semiconductor substrate. The dielectric layer has a first and a second trench. A gate dielectric layer is formed in the first and second trench. A first barrier layer is formed overlying the gate dielectric layer. A work function material layer is formed within the trenches. The work function material layer and the first barrier layer are recessed in the first and second trench. The work function material layer and the first barrier layer form a beveled surface. The gate dielectric layer is recessed in the first and second trench. A conductive gate electrode material is deposited such that it fills the first and second trench. The conductive gate electrode material is recessed in the first and second trench.

Abstract translation: 提供了具有提高的阈值电压性能的替换金属栅极的集成电路以及用于制造这种集成电路的方法。 一种方法包括提供覆盖半导体衬底的电介质层。 电介质层具有第一和第二沟槽。 栅电介质层形成在第一和第二沟槽中。 形成覆盖栅介电层的第一阻挡层。 工作功能材料层形成在沟槽内。 功函数材料层和第一阻挡层在第一和第二沟槽中凹进。 工作功能材料层和第一阻挡层形成斜面。 栅极电介质层凹入第一和第二沟槽。 沉积导电栅电极材料，使得其填充第一和第二沟槽。 导电栅电极材料凹入第一和第二沟槽。

公开(公告)号：US20150221726A1

公开(公告)日：2015-08-06

申请号：US14172362

申请日：2014-02-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoong Shing Wong ,  Min-hwa Chi ,  Tae-Hoon Kim

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A FinFET has shaped epitaxial structures for the source and drain that are electrically isolated from the substrate. Shaped epitaxial structures in the active region are separated from the substrate in the source and drain regions while those in the channel region remain. The gaps created by the separation in the source and drain are filled with electrically insulating material. Prior to filling the gaps, defects created by the separation may be reduced.

Abstract translation: FinFET已经形成了与衬底电隔离的源极和漏极的外延结构。 有源区中的形状外延结构与源极和漏极区中的衬底分离，而沟道区中的形状外延结构保留。 由源极和漏极中的分离产生的间隙填充有电绝缘材料。 在填充间隙之前，可以减少由分离产生的缺陷。

公开(公告)号：US20150099336A1

公开(公告)日：2015-04-09

申请号：US14570049

申请日：2014-12-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Hoong Shing Wong ,  Min-hwa Chi

IPC: H01L21/8234

CPC classification number: H01L21/823418 ,  H01L21/823431 ,  H01L21/823821

Abstract: Methods of manufacturing semiconductor integrated circuits having FinFET structures with epitaxially formed source and drain regions are disclosed. A method of fabricating an integrated circuit includes forming a plurality of silicon fin structures on a semiconductor substrate, epitaxially growing a silicon material on the fin structures, wherein a merged source/drain region is formed on the fin structures, and anisotropically etching at least one of the merged source drain regions to form an un-merged source/drain region.

Abstract translation: 公开了具有外延形成的源极和漏极区域的FinFET结构的半导体集成电路的制造方法。 一种制造集成电路的方法包括在半导体衬底上形成多个硅鳍结构，在翅片结构上外延生长硅材料，其中在翅片结构上形成合并的源极/漏极区，并且各向异性地蚀刻至少一个 的合并源极漏极区域以形成未合并的源极/漏极区域。

公开(公告)号：US08940650B2

公开(公告)日：2015-01-27

申请号：US13787521

申请日：2013-03-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Huy Cao ,  Huang Liu ,  Hoong Shing Wong ,  Songkram Srivathanakul ,  Sandeep Gaan

IPC: H01L21/31 ,  H01L21/02

CPC classification number: H01L21/02274 ,  H01L21/0217

Abstract: A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles.

Abstract translation: 一种制造集成电路的方法包括以下步骤：提供包括设置在其上的半导体器件的半导体衬底，并且使用第一沉积工艺在半导体衬底之上和半导体器件上沉积第一氮化硅层。 第一沉积工艺是在多个循环中操作的等离子体增强化学气相沉积（PECVD）工艺，每个循环具有第一时间间隔和第二时间间隔。 PECVD方法包括以下步骤：在第一时间间隔期间产生具有电源的等离子体，等离子体包括提供硅的气体和提供供给气体的反应性离子和自由基物质，并且在第二时间期间停止产生等离子体 间隔紧随着第一个时间间隔。 该方法还包括在多个循环之后在第一氮化硅层上沉积第二氮化硅层。

公开(公告)号：US20140256141A1

公开(公告)日：2014-09-11

申请号：US13787521

申请日：2013-03-06

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Huy Cao ,  Huang Liu ,  Hoong Shing Wong ,  Songkram Srivathanakul ,  Sandeep Gaan

IPC: H01L21/02

CPC classification number: H01L21/02274 ,  H01L21/0217

Abstract: A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles.

Abstract translation: 一种制造集成电路的方法包括以下步骤：提供包括设置在其上的半导体器件的半导体衬底，并且使用第一沉积工艺在半导体衬底之上和半导体器件上沉积第一氮化硅层。 第一沉积工艺是在多个循环中操作的等离子体增强化学气相沉积（PECVD）工艺，每个循环具有第一时间间隔和第二时间间隔。 PECVD方法包括以下步骤：在第一时间间隔期间产生具有电源的等离子体，等离子体包括提供硅的气体和提供供给气体的反应性离子和自由基物质，并且在第二时间期间停止产生等离子体 间隔紧随着第一个时间间隔。 该方法还包括在多个循环之后在第一氮化硅层上沉积第二氮化硅层。