公开(公告)号：US20140134814A1

公开(公告)日：2014-05-15

申请号：US13674142

申请日：2012-11-12

申请人： GLOBALFOUNDRIES, INC.

发明人： Hoong Shing Wong ,  Min-hwa Chi

IPC分类号： H01L29/78

CPC分类号： H01L21/823418 ,  H01L21/823431 ,  H01L21/823821

摘要： Methods of manufacturing semiconductor integrated circuits having FinFET structures with epitaxially formed source and drain regions are disclosed. For example, a method of fabricating an integrated circuit includes forming a plurality of silicon fin structures on a semiconductor substrate, forming disposable spacers on vertical sidewalls of the fin structures, and depositing a silicon oxide material over the fins and over the disposable spacers. The method further includes anisotropically etching at least one of the fin structures and the disposable spacers on the sidewalls of the at least one fin structure, thereby leaving a void in the silicon oxide material, and etching the silicon oxide material and the disposable spacers from at least one other of the fin structures, while leaving the at least one other fin structure un-etched. Still further, the method includes epitaxially growing a silicon material in the void and on the un-etched fin structure. An un-merged source/drain region is formed in the void and a merged source/drain region is formed on the un-etched fin structure.

摘要翻译： 公开了具有外延形成的源极和漏极区域的FinFET结构的半导体集成电路的制造方法。 例如，制造集成电路的方法包括在半导体衬底上形成多个硅鳍结构，在翅片结构的垂直侧壁上形成一次性间隔物，并在氧化硅材料上方并在一次性衬垫上方沉积氧化硅材料。 该方法还包括在至少一个翅片结构的侧壁上各向异性地蚀刻翅片结构和一次性间隔物中的至少一个，从而在氧化硅材料中留下空隙，并从中将氧化硅材料和一次性间隔件从 至少另一个翅片结构，同时留下至少一个其它鳍状结构未蚀刻。 此外，该方法包括在空隙中和未蚀刻的鳍结构上外延生长硅材料。 在空隙中形成未合并的源极/漏极区，并且在未蚀刻的鳍结构上形成合并的源极/漏极区。

公开(公告)号：US09159567B1

公开(公告)日：2015-10-13

申请号：US14259497

申请日：2014-04-23

申请人： GLOBALFOUNDRIES Inc.

发明人： Changyong Xiao ,  Hoong Shing Wong ,  Deepasree Konduparthi ,  Rohit Pal

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L29/6653 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7842

摘要： A method includes providing a gate structure having a dummy gate, a first spacer along a side of the gate. The dummy gate and the spacer are removed to expose a gate dielectric. A second spacer is deposited on at least one side of a gate structure cavity and a top of the gate dielectric. A bottom portion of the second spacer is removed to expose the gate dielectric and the gate structure is wet cleaned.

摘要翻译： 一种方法包括提供具有虚拟栅极的栅极结构，沿栅极侧面的第一间隔物。 去除虚拟栅极和间隔物以露出栅极电介质。 第二间隔物沉积在栅极结构腔的至少一侧和栅极电介质的顶部。 去除第二间隔件的底部以暴露栅极电介质，并且将栅极结构湿式清洁。

公开(公告)号：US09153496B2

公开(公告)日：2015-10-06

申请号：US14570049

申请日：2014-12-15

申请人： GLOBALFOUNDRIES, INC.

发明人： Hoong Shing Wong ,  Min-hwa Chi

IPC分类号： H01L21/8234 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L21/823418 ,  H01L21/823431 ,  H01L21/823821

摘要： Methods of manufacturing semiconductor integrated circuits having FinFET structures with epitaxially formed source and drain regions are disclosed. A method of fabricating an integrated circuit includes forming a plurality of silicon fin structures on a semiconductor substrate, epitaxially growing a silicon material on the fin structures, wherein a merged source/drain region is formed on the fin structures, and anisotropically etching at least one of the merged source drain regions to form an un-merged source/drain region.

摘要翻译： 公开了具有外延形成的源极和漏极区域的FinFET结构的半导体集成电路的制造方法。 一种制造集成电路的方法包括在半导体衬底上形成多个硅鳍结构，在翅片结构上外延生长硅材料，其中在翅片结构上形成合并的源极/漏极区，并且各向异性地蚀刻至少一个 的合并源极漏极区域以形成未合并的源极/漏极区域。

公开(公告)号：US09147680B2

公开(公告)日：2015-09-29

申请号：US13943944

申请日：2013-07-17

申请人： GLOBALFOUNDRIES, Inc.

发明人： Kristina Trevino ,  Yuan-Hung Lin ,  Gabriel Padron Wells ,  Chang Ho Maeng ,  Taejoon Han ,  Hoong Shing Wong

IPC分类号： H01L27/088 ,  H01L21/28

CPC分类号： H01L27/088 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

摘要： Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating such integrated circuits are provided. A method includes providing a dielectric layer overlying a semiconductor substrate. The dielectric layer has a first and a second trench. A gate dielectric layer is formed in the first and second trench. A first barrier layer is formed overlying the gate dielectric layer. A work function material layer is formed within the trenches. The work function material layer and the first barrier layer are recessed in the first and second trench. The work function material layer and the first barrier layer form a beveled surface. The gate dielectric layer is recessed in the first and second trench. A conductive gate electrode material is deposited such that it fills the first and second trench. The conductive gate electrode material is recessed in the first and second trench.

摘要翻译： 提供了具有提高的阈值电压性能的替换金属栅极的集成电路以及用于制造这种集成电路的方法。 一种方法包括提供覆盖半导体衬底的电介质层。 电介质层具有第一和第二沟槽。 栅电介质层形成在第一和第二沟槽中。 形成覆盖栅介电层的第一阻挡层。 工作功能材料层形成在沟槽内。 功函数材料层和第一阻挡层在第一和第二沟槽中凹进。 工作功能材料层和第一阻挡层形成斜面。 栅极电介质层凹入第一和第二沟槽。 沉积导电栅电极材料，使得其填充第一和第二沟槽。 导电栅电极材料凹入第一和第二沟槽。

公开(公告)号：US20150221726A1

公开(公告)日：2015-08-06

申请号：US14172362

申请日：2014-02-04

申请人： GLOBALFOUNDRIES Inc.

发明人： Hoong Shing Wong ,  Min-hwa Chi ,  Tae-Hoon Kim

IPC分类号： H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0653 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： A FinFET has shaped epitaxial structures for the source and drain that are electrically isolated from the substrate. Shaped epitaxial structures in the active region are separated from the substrate in the source and drain regions while those in the channel region remain. The gaps created by the separation in the source and drain are filled with electrically insulating material. Prior to filling the gaps, defects created by the separation may be reduced.

摘要翻译： FinFET已经形成了与衬底电隔离的源极和漏极的外延结构。 有源区中的形状外延结构与源极和漏极区中的衬底分离，而沟道区中的形状外延结构保留。 由源极和漏极中的分离产生的间隙填充有电绝缘材料。 在填充间隙之前，可以减少由分离产生的缺陷。

公开(公告)号：US20150099336A1

公开(公告)日：2015-04-09

申请号：US14570049

申请日：2014-12-15

申请人： GLOBALFOUNDRIES, INC.

发明人： Hoong Shing Wong ,  Min-hwa Chi

IPC分类号： H01L21/8234

CPC分类号： H01L21/823418 ,  H01L21/823431 ,  H01L21/823821

摘要： Methods of manufacturing semiconductor integrated circuits having FinFET structures with epitaxially formed source and drain regions are disclosed. A method of fabricating an integrated circuit includes forming a plurality of silicon fin structures on a semiconductor substrate, epitaxially growing a silicon material on the fin structures, wherein a merged source/drain region is formed on the fin structures, and anisotropically etching at least one of the merged source drain regions to form an un-merged source/drain region.

摘要翻译： 公开了具有外延形成的源极和漏极区域的FinFET结构的半导体集成电路的制造方法。 一种制造集成电路的方法包括在半导体衬底上形成多个硅鳍结构，在翅片结构上外延生长硅材料，其中在翅片结构上形成合并的源极/漏极区，并且各向异性地蚀刻至少一个 的合并源极漏极区域以形成未合并的源极/漏极区域。

公开(公告)号：US08940650B2

公开(公告)日：2015-01-27

申请号：US13787521

申请日：2013-03-06

申请人： GLOBALFOUNDRIES, Inc.

发明人： Huy Cao ,  Huang Liu ,  Hoong Shing Wong ,  Songkram Srivathanakul ,  Sandeep Gaan

IPC分类号： H01L21/31 ,  H01L21/02

CPC分类号： H01L21/02274 ,  H01L21/0217

摘要： A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles.

摘要翻译： 一种制造集成电路的方法包括以下步骤：提供包括设置在其上的半导体器件的半导体衬底，并且使用第一沉积工艺在半导体衬底之上和半导体器件上沉积第一氮化硅层。 第一沉积工艺是在多个循环中操作的等离子体增强化学气相沉积（PECVD）工艺，每个循环具有第一时间间隔和第二时间间隔。 PECVD方法包括以下步骤：在第一时间间隔期间产生具有电源的等离子体，等离子体包括提供硅的气体和提供供给气体的反应性离子和自由基物质，并且在第二时间期间停止产生等离子体 间隔紧随着第一个时间间隔。 该方法还包括在多个循环之后在第一氮化硅层上沉积第二氮化硅层。

公开(公告)号：US20140256141A1

公开(公告)日：2014-09-11

申请号：US13787521

申请日：2013-03-06

申请人： GLOBALFOUNDRIES, INC.

发明人： Huy Cao ,  Huang Liu ,  Hoong Shing Wong ,  Songkram Srivathanakul ,  Sandeep Gaan

IPC分类号： H01L21/02

CPC分类号： H01L21/02274 ,  H01L21/0217

摘要： A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles.

摘要翻译： 一种制造集成电路的方法包括以下步骤：提供包括设置在其上的半导体器件的半导体衬底，并且使用第一沉积工艺在半导体衬底之上和半导体器件上沉积第一氮化硅层。 第一沉积工艺是在多个循环中操作的等离子体增强化学气相沉积（PECVD）工艺，每个循环具有第一时间间隔和第二时间间隔。 PECVD方法包括以下步骤：在第一时间间隔期间产生具有电源的等离子体，等离子体包括提供硅的气体和提供供给气体的反应性离子和自由基物质，并且在第二时间期间停止产生等离子体 间隔紧随着第一个时间间隔。 该方法还包括在多个循环之后在第一氮化硅层上沉积第二氮化硅层。

公开(公告)号：US09337340B2

公开(公告)日：2016-05-10

申请号：US14656649

申请日：2015-03-12

申请人： GLOBALFOUNDRIES Inc.

发明人： Min-Hwa Chi ,  Hoong Shing Wong

IPC分类号： H01L29/78 ,  H01L29/22 ,  H01L29/20 ,  H01L29/66

CPC分类号： H01L29/7853 ,  H01L29/20 ,  H01L29/22 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor structure in fabrication includes a n-FinFET and p-FinFET. Stress inducing materials such as silicon and silicon germanium are epitaxially grown into naturally diamond-shaped structures atop the silicon fins of the n-FinFET and p-FinFET areas. The diamond structures act as the source, drain and channel between the source and drain. The diamond structures of the channel are selectively separated from the fin while retaining the fin connections of the diamond-shaped growth of the source and the drain. Further fabrication to complete the structure may then proceed.

公开(公告)号：US09252238B1

公开(公告)日：2016-02-02

申请号：US14461887

申请日：2014-08-18

申请人： GLOBALFOUNDRIES Inc.

发明人： Kristina Trevino ,  Yuan-Hung Liu ,  Gabriel Padron Wells ,  Xing Zhang ,  Hoong Shing Wong ,  Chang Ho Maeng ,  Taejoon Han ,  Gowri Kamarthy ,  Isabelle Orain ,  Ganesh Upadhyaya

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L21/3213 ,  H01L29/40

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32136 ,  H01L29/4966 ,  H01L29/517

摘要： Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.

摘要翻译： 提供半导体结构和制造方法，其包括例如在半导体衬底上提供栅极结构，所述栅极结构包括多个共形栅极层和设置在多个共形栅极层内的栅极材料; 将多个共形栅极层的一部分凹陷在栅极结构的上表面之下，其中凹入的多个共形栅极层的上表面是共面的; 以及去除所述栅极材料的一部分以便于所述栅极材料的剩余部分的上表面与所述凹入的多个共形栅极层的上表面共面。