公开(公告)号：US10043764B2

公开(公告)日：2018-08-07

申请号：US15247513

申请日：2016-08-25

申请人： GLOBALFOUNDRIES INC.

发明人： Huang Liu ,  Sarasvathi Thangaraju ,  Chun Yu Wong

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498 ,  H01L25/07

摘要： Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress, thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

公开(公告)号：US09627274B1

公开(公告)日：2017-04-18

申请号：US15214670

申请日：2016-07-20

申请人： GLOBALFOUNDRIES Inc.

发明人： Haifeng Sheng ,  Xintuo Dai ,  Jinping Liu ,  Huang Liu

IPC分类号： H01L21/8238 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/786 ,  H01L21/84 ,  H01L29/78

CPC分类号： H01L21/823871 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856 ,  H01L29/786

摘要： One illustrative method disclosed herein includes, among other things, forming a first sacrificial layer comprising amorphous silicon or polysilicon material around a fin in a lateral space between a plurality of laterally spaced apart gate structures that are positioned around the fin, performing a first selective etching process to remove a first sacrificial layer selectively relative to surrounding material so as to expose the fin in the lateral space, forming an epi material on the exposed portion of the fin, and forming a second layer of a sacrificial material above the epi material. The method also includes selectively removing the second layer of sacrificial material relative to at least the first layer of material to thereby define a source/drain contact opening that exposes the epi material and forming a self-aligned trench conductive source/drain contact structure that is conductively coupled to the epi material.

公开(公告)号：US09620381B2

公开(公告)日：2017-04-11

申请号：US14050472

申请日：2013-10-10

申请人： GLOBALFOUNDRIES Inc.

发明人： Suraj K. Patil ,  Huy Cao ,  Hui Zhan ,  Huang Liu

IPC分类号： H01L21/311 ,  H01L29/66 ,  H01L21/3115

CPC分类号： H01L21/31105 ,  H01L21/31116 ,  H01L21/31155 ,  H01L29/66795

摘要： Methods of facilitating fabrication of circuit structures are provided which include, for instance: providing a structure with a film layer; modifying an etch property of the film layer by implanting at least one species of element or molecule into the upper portion of the film layer, the etch property of the film layer remaining unmodified beneath the upper portion; and subjecting the structure and film layer with the modified etch property to an etching process, the modified etch property of the film layer facilitating the etching process. Modifying the etch property of the upper portion of the film layer may include making the upper portion of the film layer preferentially susceptible or preferentially resistant to the etching process depending on the circuit fabrication approach being facilitated.

公开(公告)号：US09455188B2

公开(公告)日：2016-09-27

申请号：US13744551

申请日：2013-01-18

申请人： GLOBALFOUNDRIES Inc.

发明人： Huang Liu ,  Sarasvathi Thangaraju ,  Chun Yu Wong

IPC分类号： H01L23/48 ,  H01L21/336 ,  H01L21/768

CPC分类号： H01L23/562 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49894 ,  H01L25/072 ,  H01L2924/0002 ,  H01L2924/00

摘要： Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress, thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

摘要翻译： 本发明的方面通常涉及用于形成半导体器件的方法，例如在TSV和晶体管之间具有“缓冲区”或间隙层的TSV器件。 间隙层通常填充有低应力的薄膜填充材料，其控制装置上的应力和裂纹形成。 此外，间隙层确保TSV和晶体管之间的一定空间距离，以减少温度偏移的不利影响。

公开(公告)号：US09368342B2

公开(公告)日：2016-06-14

申请号：US14252447

申请日：2014-04-14

申请人： GLOBALFOUNDRIES Inc.

发明人： Haigou Huang ,  Huang Liu ,  Jin Ping Liu

IPC分类号： H01L21/02 ,  H01L21/311 ,  H01L21/306

CPC分类号： H01L21/02381 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31053 ,  H01L21/31111

摘要： A defect-free, relaxed semiconductor covering layer (e.g., epitaxial SiGe) over a semiconductor substrate (e.g., Si) is provided having a strain relaxation degree above about 80% and a non-zero threading dislocation density of less than about 100/cm2. A lattice mismatch exists between the substrate and the covering layer. The covering layer also has a non-zero thickness that may be less than about 0.5 microns. The strain relaxation degree and threading dislocation are achieved by exposing defects at or near a surface of an initial semiconductor layer on the substrate (i.e., exposing defects via selective etch and filling-in any voids created), planarizing the filled-in surface, and creating the covering layer (e.g., growing epitaxy) on the planarized, filled-in surface, which is also planarized.

摘要翻译： 提供半导体衬底（例如Si）上的无缺陷的，松弛的半导体覆盖层（例如，外延SiGe），其具有高于约80％的应变松弛度和小于约100 / cm 2的非零穿透位错密度 。 衬底和覆盖层之间存在晶格失配。 覆盖层还具有可以小于约0.5微米的非零厚度。 应变松弛度和穿透位错是通过在基板上的初始半导体层的表面处或附近暴露缺陷来实现的（即，通过选择性蚀刻暴露缺陷并填充所产生的任何空隙），平坦化填充表面，以及 在平坦化的填充表面上形成覆盖层（例如，生长外延），其也被平坦化。

公开(公告)号：US20160163830A1

公开(公告)日：2016-06-09

申请号：US14560035

申请日：2014-12-04

申请人： GLOBALFOUNDRIES, Inc.

发明人： Hong Yu ,  Jin Ping Liu ,  Haigou Huang ,  Huang Liu

IPC分类号： H01L29/66 ,  H01L21/3105 ,  H01L21/02

CPC分类号： H01L29/66795 ,  H01L21/02326 ,  H01L21/31053 ,  H01L21/31111 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636

摘要： A method includes forming at least one fin in a semiconductor substrate. A placeholder gate structure is formed above the fin. The placeholder gate structure includes a placeholder material and a cap structure defined on a top surface of the placeholder material. The cap structure includes a first cap layer disposed above the placeholder material and a second cap layer disposed above the first cap layer. An oxidization process is performed on at least a portion of the second cap layer to form an oxidized region above a remaining portion of the second cap layer. A portion of the oxidized region is removed to expose the remaining portion. The remaining portion of the second cap layer is removed. The first cap layer is removed to expose the placeholder material. The placeholder material is replaced with a conductive material.

摘要翻译： 一种方法包括在半导体衬底中形成至少一个翅片。 在翅片上形成占位符门结构。 占位符门结构包括在占位符材料的顶表面上限定的占位符材料和盖结构。 盖结构包括设置在占位符材料上方的第一盖层和设置在第一盖层上方的第二盖层。 在第二盖层的至少一部分上进行氧化处理，以在第二盖层的剩余部分上方形成氧化区域。 去除氧化区域的一部分以露出剩余部分。 去除第二盖层的剩余部分。 移除第一盖层以露出占位符材料。 占位符材料被导电材料代替。

公开(公告)号：US20140175562A1

公开(公告)日：2014-06-26

申请号：US13727218

申请日：2012-12-26

申请人： GLOBALFOUNDRIES, INC.

发明人： Haiting Wang ,  Huang Liu ,  Yong Meng Lee ,  Songkram Srivathanakul

IPC分类号： H01L21/28 ,  H01L29/423

CPC分类号： H01L29/6653 ,  H01L21/76837 ,  H01L21/823468 ,  H01L21/823864

摘要： A semiconductor structure in fabrication includes a NFET and a PFET. Spacers adjacent gate structures of the NFET and PFET have undesired divots that can lead to substrate damage from chemicals used in a subsequent etch. The fabrication also leaves hard masks over the gate structures with non-uniform height. The divots are filled with material resistant to the chemicals used in the etch. Excess filler is removed, and uniform height is restored. Further fabrication may then proceed.

摘要翻译： 制造中的半导体结构包括NFET和PFET。 NFET和PFET的相邻栅极结构的间隔具有不期望的凹陷，这可能导致在后续蚀刻中使用的化学品的基底损伤。 该制造也在具有不均匀高度的门结构上留下硬掩模。 这些图案填充有耐蚀刻中使用的化学品的材料。 去除多余的填料，恢复均匀的高度。 然后进一步制造。

公开(公告)号：US10559470B2

公开(公告)日：2020-02-11

申请号：US15876407

申请日：2018-01-22

申请人： GLOBALFOUNDRIES INC.

发明人： Haigou Huang ,  Jinsheng Gao ,  Hong Yu ,  Jinping Liu ,  Huang Liu

IPC分类号： H01L27/08 ,  H01L21/28 ,  H01L21/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/311 ,  H01L21/768

摘要： The present disclosure relates to semiconductor structures and, more particularly, to capping structures and methods of manufacture. The structure includes: a plurality of gate structures in a first location with a first density; a plurality of gate structures in a second location with a second density different than the first density; and a T-shaped capping structure protecting the plurality of gate structures in the first location and in the second location.

公开(公告)号：US10056458B2

公开(公告)日：2018-08-21

申请号：US14993537

申请日：2016-01-12

申请人： GLOBALFOUNDRIES Inc.

发明人： Chang Ho Maeng ,  Andy Wei ,  Anthony Ozzello ,  Bharat Krishnan ,  Guillaume Bouche ,  Haifeng Sheng ,  Haigou Huang ,  Huang Liu ,  Huy M. Cao ,  Ja-Hyung Han ,  SangWoo Lim ,  Kenneth A. Bates ,  Shyam Pal ,  Xintuo Dai ,  Jinping Liu

IPC分类号： H01L21/3205 ,  H01L29/40 ,  H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L29/417

CPC分类号： H01L29/401 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/28229 ,  H01L21/76828 ,  H01L21/76837 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/78

摘要： Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.

公开(公告)号：US09606432B2

公开(公告)日：2017-03-28

申请号：US14533464

申请日：2014-11-05

申请人： GLOBALFOUNDRIES INC.

发明人： Guoxiang Ning ,  Xintuo Dai ,  Huang Liu ,  Chin Teong Lim

IPC分类号： G03F7/00 ,  G03F7/09 ,  G03F7/20

CPC分类号： G03F7/0035 ,  G03F7/094 ,  G03F7/2024 ,  G03F7/203

摘要： Fabrication of a circuit structure is facilitated, in which a first exposure of a multi-layer structure is performed using a first mask, which defines positioning of at least one edge of an element to be formed above a substrate of the multi-layer structure. A second exposure of the multi-layer structure is performed using a second mask, which defines positioning of at least one other edge of the element. At least some material of the multi-layer structure is removed using, at least in part, the defined positioning of the at least one edge and the at least one other edges of the element, to form the element above the substrate. In some examples, multiple elements are formed, the multiple elements being hardmask elements to facilitate an etch process to etch a substrate material.