公开(公告)号：US20150287795A1

公开(公告)日：2015-10-08

申请号：US14244261

申请日：2014-04-03

申请人： GLOBALFOUNDRIES, Inc.

发明人： Sandeep Gaan ,  Sipeng Gu

IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311

CPC分类号： H01L29/66795 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/41791 ,  H01L29/785

摘要： Processes for preparing an integrated circuit for contact landing, processes for fabricating an integrated circuit, and integrated circuits prepared according to these processes are provided herein. An exemplary process for preparing an integrated circuit for contact landing includes providing a semiconductor structure that includes a transistor with source and drain regions, wherein at least one of the source and drain regions has a shaped contact structure overlaid with a contact etch stop layer and a pre-metal dielectric material. The pre-metal dielectric material is removed with one or more anisotropic etches, including at least one anisotropic etch selective to the pre-metal dielectric material. And, the contact etch stop layer overlaying the shaped contact structure is removed with a third anisotropic etch selective to the contact etch stop layer material to expose the shaped contact structure.

摘要翻译： 本文提供了用于制备用于接触着陆的集成电路，用于制造集成电路的工艺，以及根据这些工艺制备的集成电路的工艺。 用于制备用于接触着陆的集成电路的示例性方法包括提供包括具有源区和漏区的晶体管的半导体结构，其中源极和漏极区中的至少一个具有覆盖有接触蚀刻停止层的成形接触结构和 预金属介电材料。 用一种或多种各向异性蚀刻去除预金属介电材料，包括对前金属介电材料选择性的至少一种各向异性蚀刻。 并且，用接触蚀刻停止层材料选择性的第三各向异性蚀刻去除覆盖成形接触结构的接触蚀刻停止层，以露出成形的接触结构。

公开(公告)号：US20180040505A1

公开(公告)日：2018-02-08

申请号：US15225994

申请日：2016-08-02

申请人： GLOBALFOUNDRIES Inc.

发明人： Sandeep Gaan ,  Shishir Ray ,  Vikrant Chauhan

IPC分类号： H01L21/762 ,  H01L21/324

CPC分类号： H01L21/76283 ,  H01L21/324

摘要： A method includes forming a trench in a stack comprising a substrate, a buried oxide layer formed above the substrate, a semiconductor layer formed above the buried oxide layer and a hard mask layer formed above the semiconductor layer. A first liner is formed in the trench. A first oxide layer is formed in the trench. A diffusionless anneal process is performed to densify the first oxide layer. The first oxide layer is recessed to define a recess. A second oxide layer is formed in the recess.

公开(公告)号：US09570291B2

公开(公告)日：2017-02-14

申请号：US14798796

申请日：2015-07-14

申请人： GLOBALFOUNDRIES, Inc.

发明人： Shishir Ray ,  Sandeep Gaan ,  Sheldon Meyers ,  Nisha Pillai ,  Edmund Kenneth Banghart ,  Kyle Jung

IPC分类号： G03F7/26 ,  H01L21/02 ,  H01L29/16

CPC分类号： H01L29/1604 ,  H01L21/02592 ,  H01L21/02675 ,  H01L21/268 ,  H01L21/31058

摘要： Semiconductor substrates and methods for processing semiconductor substrates are provided. A method for processing a semiconductor substrate includes providing a semiconductor substrate having an outer edge, a central region, and a peripheral region between the outer edge and the central region. The semiconductor substrate also has an upper surface. The method includes forming an amorphous material over the upper surface of the semiconductor substrate in the peripheral region. Also, the method includes irradiating the upper surface of the semiconductor substrate, wherein the amorphous material inhibits cracking at the outer edge of the semiconductor substrate.

摘要翻译： 提供半导体衬底和半导体衬底的处理方法。 一种用于处理半导体衬底的方法包括提供在外边缘和中心区域之间具有外边缘，中心区域和周边区域的半导体衬底。 半导体衬底也具有上表面。 该方法包括在周边区域的半导体衬底的上表面上形成无定形材料。 此外，该方法包括照射半导体衬底的上表面，其中非晶态材料抑制在半导体衬底的外边缘处的裂纹。

公开(公告)号：US20170018426A1

公开(公告)日：2017-01-19

申请号：US14798796

申请日：2015-07-14

申请人： GLOBALFOUNDRIES, Inc.

发明人： Shishir Ray ,  Sandeep Gaan ,  Sheldon Meyers ,  Nisha Pillai ,  Edmund Kenneth Banghart ,  Kyle Jung

IPC分类号： H01L21/02 ,  H01L29/16

CPC分类号： H01L29/1604 ,  H01L21/02592 ,  H01L21/02675 ,  H01L21/268 ,  H01L21/31058

摘要： Semiconductor substrates and methods for fabricating integrated circuits are provided. A method for fabricating an integrated circuit includes providing a semiconductor substrate having an outer edge, a central region, and a peripheral region between the outer edge and the central region. The semiconductor substrate also has an upper surface. The method includes forming an amorphous material over the upper surface of the semiconductor substrate in the peripheral region. Also, the method includes irradiating the upper surface of the semiconductor substrate, wherein the amorphous material inhibits cracking at the outer edge of the semiconductor substrate.

摘要翻译： 提供半导体基板和用于制造集成电路的方法。 一种用于制造集成电路的方法包括提供在外边缘和中心区域之间具有外边缘，中心区域和周边区域的半导体基板。 半导体衬底也具有上表面。 该方法包括在周边区域的半导体衬底的上表面上形成无定形材料。 此外，该方法包括照射半导体衬底的上表面，其中非晶态材料抑制在半导体衬底的外边缘处的裂纹。

公开(公告)号：US20150333121A1

公开(公告)日：2015-11-19

申请号：US14810167

申请日：2015-07-27

申请人： GLOBALFOUNDRIES INC.

发明人： Hongliang Shen ,  Kyutae Na ,  Sandeep Gaan ,  Hsin-Neng Tai ,  Weihua Tong ,  Sang Cheol Han ,  Tae Hoon Kim ,  Ja Hyung Han ,  Haigou Huang ,  Changyong Xiao ,  Huang Liu ,  Seung Yeon Kim

IPC分类号： H01L29/06 ,  H01L27/088

CPC分类号： H01L29/0649 ,  H01L21/02123 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/0886

摘要： Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

摘要翻译： 本发明的方面通常涉及用于形成半导体器件的方法，例如在TSV和晶体管之间具有“缓冲区”或间隙层的TSV器件。 间隙层通常填充有低应力薄膜填充材料，其控制器件上的应力和裂纹形成。 此外，间隙层确保TSV和晶体管之间的一定空间距离，以减少温度偏移的不利影响。

公开(公告)号：US09831098B2

公开(公告)日：2017-11-28

申请号：US14797337

申请日：2015-07-13

申请人： GLOBALFOUNDRIES, Inc.

发明人： Xinyuan Dou ,  Sukwon Hong ,  Satyajit Shinde ,  Sandeep Gaan ,  Tao Han ,  Carlos Chacon ,  Shimpei Yamaguchi

IPC分类号： H01L21/3105 ,  H01L29/423 ,  H01L29/66 ,  H01L21/762

CPC分类号： H01L21/3105 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/76229 ,  H01L29/42356 ,  H01L29/66795

摘要： Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an isolation trench between two fin structures on an integrated circuit substrate, forming a flowable film in the isolation trench using a flowable chemical vapor deposition process, and annealing the flowable film to form a silicon oxide dielectric layer in the isolation trench. The annealing is performed at a temperature of less than about 200° C. with a process gas including N2 and H2O2.

公开(公告)号：US09385192B2

公开(公告)日：2016-07-05

申请号：US14810167

申请日：2015-07-27

申请人： GLOBALFOUNDRIES Inc.

发明人： Hongliang Shen ,  Kyutae Na ,  Sandeep Gaan ,  Hsin-Neng Tai ,  Weihua Tong ,  Sang Cheol Han ,  Tae Hoon Kim ,  Ja Hyung Han ,  Haigou Huang ,  Changyong Xiao ,  Huang Liu ,  Seung Yeon Kim

IPC分类号： H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L27/088

CPC分类号： H01L29/0649 ,  H01L21/02123 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/0886

摘要： Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

公开(公告)号：US09224842B2

公开(公告)日：2015-12-29

申请号：US14258488

申请日：2014-04-22

申请人： GLOBALFOUNDRIES Inc.

发明人： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Xiang Hu ,  Jerome F. Wandell ,  Sandeep Gaan

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L21/02488 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.

摘要翻译： 提供了使用存储层在半导体器件中图案化多个致密特征的方法。 具体地，一种方法包括：在存储层中图形化多个开口; 在所述多个开口的每一个内形成间隙填充材料; 去除记忆层; 去除邻近间隙填充材料的蚀刻停止层，其中蚀刻停止层的一部分保留在间隙填充材料的下面; 蚀刻硬掩模以在所述一组栅极结构之上形成一组开口，其中对所述硬掩模的蚀刻还从所述蚀刻停止层的剩余部分顶部除去所述间隙填充材料; 并蚀刻半导体器件以去除每组开口内的硬掩模。 在一个实施例中，然后通过蚀刻对栅极结构有选择性的电介质层，在半导体器件的一组鳍片上形成一组虚拟S / D接触柱。

公开(公告)号：US09184288B2

公开(公告)日：2015-11-10

申请号：US14207822

申请日：2014-03-13

申请人： GLOBALFOUNDRIES Inc.

发明人： Sipeng Gu ,  Zhiguo Sun ,  Sandeep Gaan ,  Danni Chen ,  Wen-Pin Peng ,  Huang Liu

IPC分类号： H01L21/8238 ,  H01L29/78 ,  H01L29/40 ,  H01L21/02

CPC分类号： H01L29/7843 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02205 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/76801 ,  H01L21/76829 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： Semiconductor structures and fabrication methods are provided having a bridging film which facilitates adherence of both an underlying layer of dielectric material and an overlying stress-inducing layer. The method includes, for instance, providing a layer of dielectric material, with at least one gate structure disposed therein, over a semiconductor substrate; providing a bridging film over the layer of dielectric material with the at least one gate structure; and providing a stress-inducing layer over the bridging film. The bridging film is selected to facilitate adherence of both the underlying layer of dielectric material and the overlying stress-inducing layer by, in part, forming a chemical bond with the layer of dielectric material, without forming a chemical bond with the stress-inducing layer.

摘要翻译： 提供半导体结构和制造方法，其具有桥接膜，其有助于介电材料的下层和上覆的应力诱导层的粘附。 该方法包括例如在半导体衬底上提供其中设置有至少一个栅极结构的电介质材料层; 在所述介​​电材料层上提供具有所述至少一个栅极结构的桥接膜; 并在桥接膜上提供应力诱导层。 选择桥接膜以便于通过部分地与电介质材料层形成化学键而使介电材料的下层和上覆的应力诱导层两者粘附，而不与应力诱导层形成化学键 。

公开(公告)号：US09123771B2

公开(公告)日：2015-09-01

申请号：US13765723

申请日：2013-02-13

申请人： GLOBALFOUNDRIES Inc.

发明人： Hongliang Shen ,  Kyutae Na ,  Sandeep Gaan ,  Hsin-Neng Tai ,  Weihua Tong ,  Sang Cheol Han ,  Tae Hoon Kim ,  Ja Hyung Han ,  Haigou Huang ,  Changyong Xiao ,  Huang Liu ,  Seung Yeon Kim

IPC分类号： H01L21/762 ,  H01L21/02

CPC分类号： H01L29/0649 ,  H01L21/02123 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/0886

摘要： Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

摘要翻译： 本发明的方面通常涉及用于形成半导体器件的方法，例如在TSV和晶体管之间具有“缓冲区”或间隙层的TSV器件。 间隙层通常填充有低应力薄膜填充材料，其控制器件上的应力和裂纹形成。 此外，间隙层确保TSV和晶体管之间的一定空间距离，以减少温度偏移的不利影响。