公开(公告)号：US09337082B2

公开(公告)日：2016-05-10

申请号：US13744756

申请日：2013-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Junjing Bao ,  Wai-Kin Li

IPC: H01L23/48 ,  H01L21/336 ,  H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/7684

Abstract: A dielectric material stack including at least a via level dielectric material layer, at least one patterned etch stop dielectric material portion, a line level dielectric material layer, and optionally a dielectric cap layer is formed over a substrate. At least one patterned hard mask layer including a first pattern can be formed above the dielectric material stack. A second pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure. The first pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure while the second pattern is transferred through the via level dielectric material layer to form integrated line and via trenches, which are filled with a conductive material to form integrated line and via structures.

Abstract translation: 包括至少一个通孔级电介质材料层，至少一个图案化的蚀刻停止介电材料部分，一行电介质材料层和任选的电介质盖层的电介质材料堆叠在衬底上。 包括第一图案的至少一个图案化的硬掩模层可以形成在介电材料堆叠的上方。 使用至少一个蚀刻停止介电材料部分作为蚀刻停止结构，通过线路电介质材料层转移第二图案。 第一图案通过采用至少一个蚀刻停止介电材料部分的线路电介质材料层转移作为蚀刻停止结构，而第二图案通过通孔级电介质材料层转移以形成集成线和通孔沟槽， 填充导电材料以形成集成线路和通孔结构。

公开(公告)号：US09559051B1

公开(公告)日：2017-01-31

申请号：US14976417

申请日：2015-12-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yongchun Xin ,  Jang H. Sim ,  Junjing Bao ,  Zhigang Song ,  Yunsheng Song

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/3205 ,  H01L21/3213 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/32055 ,  H01L21/32137 ,  H01L21/76804 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76879 ,  H01L23/53238 ,  H01L2221/1063

Abstract: A method for depositing a conductor in the via opening electronic structure removes the via bottom liner so that the conductor deposited in the via opening directly contacts the underlying conductive layer. The method includes depositing amorphous silicon over the dielectric layer and the liner layer on the via opening sidewalls and bottom. The amorphous silicon extends substantially over the entire via opening while leaving below a void within the via opening. The amorphous silicon over the via opening and on the via opening bottom and the liner layer on the via opening bottom are anisotropically etched to leave a layer of amorphous silicon over the dielectric layer and the via opening side walls. The amorphous silicon is then removed to form a via opening having a substantially open-bottom liner. The conductor is then deposited in the via opening and contacts the underlying conductive layer.

Abstract translation: 用于在通孔开口电子结构中沉积导体的方法去除了通孔底部衬垫，使得沉积在通孔开口中的导体直接接触下面的导电层。 该方法包括在通孔开口侧壁和底部上的绝缘层和衬垫层上沉积非晶硅。 非晶硅基本上在整个通孔开口上延伸，同时在通孔开口内留下空隙。 在通孔开口和通孔开口底部和通孔开口底部上的衬垫层上的非晶硅被各向异性地蚀刻，以在电介质层和通孔开口侧壁上留下一层非晶硅。 然后去除非晶硅以形成具有基本上开口底部衬垫的通孔。 然后将导体沉积在通孔开口中并接触下面的导电层。