公开(公告)号：US09755016B2

公开(公告)日：2017-09-05

申请号：US15088592

申请日：2016-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Samuel S. Choi ,  Wai-Kin Li

IPC: H01L23/52 ,  H01L29/06 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L23/525 ,  H01L21/768

CPC classification number: H01L29/0657 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76229 ,  H01L21/76816 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to transferring, in one exposure, a single-mask feature to form two features on an underlying material. Specifically, a doubled walled structure (i.e. a center opening flanked by adjacent openings) is formed. Advantageously, the openings may be sub-resolution openings. The center opening may be a line flanked by two other lines. The center opening may be circular and surrounded by an outer ring, thus forming a double wall ring structure. In an electronic fuse embodiment, the double wall ring structure is a via filled with a conductor that contacts a lower and upper level metal. In deep trench embodiment, the double wall ring structure is a deep trench in a semiconductor substrate filled with insulating material. In such a way the surface area of the trench is increased thereby increasing capacitance.

公开(公告)号：US09755013B2

公开(公告)日：2017-09-05

申请号：US14692881

申请日：2015-04-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wai-Kin Li ,  Chengwen Pei ,  Ping-Chuan Wang

IPC: H01L49/02 ,  H01L27/06 ,  H01L21/8238

CPC classification number: H01L28/92 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0629

Abstract: High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.

公开(公告)号：US20160322458A1

公开(公告)日：2016-11-03

申请号：US15088592

申请日：2016-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Samuel S. Choi ,  Wai-Kin Li

IPC: H01L29/06 ,  H01L23/525 ,  H01L21/311 ,  H01L21/768 ,  H01L21/033 ,  H01L21/308

CPC classification number: H01L29/0657 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76229 ,  H01L21/76816 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to transferring, in one exposure, a single-mask feature to form two features on an underlying material. Specifically, a doubled walled structure (i.e. a center opening flanked by adjacent openings) is formed. Advantageously, the openings may be sub-resolution openings. The center opening may be a line flanked by two other lines. The center opening may be circular and surrounded by an outer ring, thus forming a double wall ring structure. In an electronic fuse embodiment, the double wall ring structure is a via filled with a conductor that contacts a lower and upper level metal. In deep trench embodiment, the double wall ring structure is a deep trench in a semiconductor substrate filled with insulating material. In such a way the surface area of the trench is increased thereby increasing capacitance.

公开(公告)号：US09337261B2

公开(公告)日：2016-05-10

申请号：US13859966

申请日：2013-04-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Samuel S. Choi ,  Wai-Kin Li

IPC: H01L23/52 ,  H01L29/06 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L23/525

CPC classification number: H01L29/0657 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76229 ,  H01L21/76816 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to transferring, in one exposure, a single-mask feature to form two features on an underlying material. Specifically, a doubled walled structure (i.e. a center opening flanked by adjacent openings) is formed. Advantageously, the openings may be sub-resolution openings. The center opening may be a line flanked by two other lines. The center opening may be circular and surrounded by an outer ring, thus forming a double wall ring structure. In an electronic fuse embodiment, the double wall ring structure is a via filled with a conductor that contacts a lower and upper level metal. In deep trench embodiment, the double wall ring structure is a deep trench in a semiconductor substrate filled with insulating material. In such a way the surface area of the trench is increased thereby increasing capacitance.

Abstract translation: 本发明涉及在一次曝光中转移单掩模特征以在下面的材料上形成两个特征。 具体地说，形成了双层壁结构（即由相邻开口侧面的中心开口）。 有利地，开口可以是子分辨率开口。 中心开口可以是两条另外两条线的线。 中心开口可以是圆形的并且被外环包围，从而形成双壁环结构。 在电子熔断器实施例中，双壁环结构是通过与下层和上层金属接触的导体填充的通孔。 在深沟槽实施例中，双壁环结构是填充有绝缘材料的半导体衬底中的深沟槽。 以这种方式，沟槽的表面积增加，从而增加电容。

公开(公告)号：US10049926B2

公开(公告)日：2018-08-14

申请号：US15146510

申请日：2016-05-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Junjing Bao ,  Wai-Kin Li

IPC: H01L21/768

Abstract: A dielectric material stack including at least a via level dielectric material layer, at least one patterned etch stop dielectric material portion, a line level dielectric material layer, and optionally a dielectric cap layer is formed over a substrate. At least one patterned hard mask layer including a first pattern can be formed above the dielectric material stack. A second pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure. The first pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure while the second pattern is transferred through the via level dielectric material layer to form integrated line and via trenches, which are filled with a conductive material to form integrated line and via structures.

公开(公告)号：US20160071742A1

公开(公告)日：2016-03-10

申请号：US14942228

申请日：2015-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

IPC: H01L21/3213 ,  H01L21/311

CPC classification number: H01L21/32139 ,  G09C1/00 ,  H01L21/0273 ,  H01L21/31058 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76885 ,  H01L22/34 ,  H01L23/522 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/528 ,  H01L23/5386 ,  H01L23/544 ,  H01L23/57 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2223/5448 ,  H01L2224/05097 ,  H04L9/3278 ,  H04L2209/12

Abstract: An organic material layer is lithographically patterned to include a linear array portion of lines and spaces. In one embodiment, the organic material layer can be an organic planarization layer that is patterned employing a photoresist layer, which is consumed during patterning of the organic planarization layer. Volume expansion of the organic planarization layer upon exposure to a halogen-including gas causes portions of the linear array to collapse at random locations. In another embodiment, the height of the photoresist layer is selected such that the linear array portion of the photoresist layer is mechanically unstable and produces random photoresist collapses. The pattern including random modifications due to the collapse of the organic material layer is transferred into an underlying layer to generate an array of conductive material lines with random electrical disruption of shorts or opens. The structure with random shorts can be employed as a physical unclonable function.

公开(公告)号：US09240376B2

公开(公告)日：2016-01-19

申请号：US13968467

申请日：2013-08-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Junjing Bao ,  Samuel S. Choi ,  Wai-Kin Li

IPC: H01L23/525 ,  H01L21/768

CPC classification number: H01L23/5256 ,  H01L21/31144 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming a first via opening in a substrate, the first via opening is self-aligned to a first trench in the substrate, forming a second via opening in the substrate, the second via opening is self-aligned to a second trench in the substrate, a portion of the second via opening overlaps a portion of the first via opening to form an overlap region, and the overlap region having a width (w) equal to or greater than a space (s) between the first trench and the second trench, and removing a portion of the substrate in the overlap region to form a bridge opening, the bridge opening is adjacent to the first and second via openings and extends between the first and second trenches.

Abstract translation: 一种方法，包括在衬底中形成第一通孔，所述第一通孔开口与所述衬底中的第一沟槽自对准，在所述衬底中形成第二通孔，所述第二通孔开口自对准至第二沟槽， 所述第二通孔开口的一部分与所述第一通路孔的一部分重叠以形成重叠区域，并且所述重叠区域的宽度（w）等于或大于所述第一沟槽和所述第二通路孔之间的空间 并且在所述重叠区域中移除所述基板的一部分以形成桥开口，所述桥开口与所述第一和第二通孔相邻，并且在所述第一沟槽和所述第二沟槽之间延伸。

公开(公告)号：US09627272B2

公开(公告)日：2017-04-18

申请号：US14833813

申请日：2015-08-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huihang Dong ,  Wai-Kin Li

IPC: H01L21/3205 ,  H01L21/8238 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L21/823842 ,  H01L21/02118 ,  H01L21/28088 ,  H01L21/32139

Abstract: A patterning scheme to minimize dry/wet strip induced device degradation and resultant devices are provided. The method includes removing a workfunction material over a first device area of a structure, while protecting the workfunction material over a second device area of the structure with a first masking material. The method further includes applying a second masking material over the first device area and the first masking material. The method further includes removing the first masking material and the second masking material until the workfunction material is exposed over the second device area.

公开(公告)号：US09465290B2

公开(公告)日：2016-10-11

申请号：US14243238

申请日：2014-04-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wu-Song Huang ,  Martin Glodde ,  Dario L. Goldfarb ,  Wai-Kin Li ,  Sen Liu ,  Libor Vyklicky

IPC: C09D5/32 ,  C09D163/00 ,  C08K5/00 ,  G03F7/038 ,  G03F7/09 ,  G03F7/11 ,  H01L51/44

CPC classification number: G03F7/0388 ,  G03F7/038 ,  G03F7/091 ,  G03F7/11 ,  H01L51/447

Abstract: A curable liquid formulation comprising: (i) one or more near-infrared absorbing polymethine dyes; (ii) one or more crosslinkable polymers; and (iii) one or more casting solvents. The invention is also directed to solid near-infrared absorbing films composed of crosslinked forms of the curable liquid formulation. The invention is also directed to a microelectronic substrate containing a coating of the solid near-infrared absorbing film as well as a method for patterning a photoresist layer coated on a microelectronic substrate in the case where the near-infrared absorbing film is between the microelectronic substrate and a photoresist film.

Abstract translation: 一种可固化液体制剂，其包含：（i）一种或多种近红外吸收聚甲炔染料; （ii）一种或多种可交联聚合物; 和（iii）一种或多种浇铸溶剂。 本发明还涉及由可固化液体制剂的交联形式组成的固体近红外吸收膜。 本发明还涉及一种含有固体近红外线吸收膜的涂层的微电子衬底，以及在近红外吸收膜位于微电子衬底之间的情况下，用于图案化涂覆在微电子衬底上的光刻胶层的方法 和光刻胶膜。

公开(公告)号：US09236575B1

公开(公告)日：2016-01-12

申请号：US14478115

申请日：2014-09-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wai-Kin Li ,  Hanfei Wang

IPC: H01L51/30 ,  H01L51/40 ,  H01L51/05 ,  H01L51/00 ,  H01L51/10

CPC classification number: H01L51/0541 ,  H01L51/0012 ,  H01L51/004 ,  H01L51/0049 ,  H01L51/0093 ,  H01L51/107

Abstract: After forming a plurality of metal anchors arranged in a matrix of rows and columns and a plurality trenches separating adjacent rows of metal anchors on a substrate, a dispersion comprising charged single-wall carbon nanotubes (SWCNTs) having a surface binding group on each end of the charged SWCNTs is directed to flow through the plurality of trenches. During the flow process, one end of each of the charged SWCNTs binds to a corresponding metal anchor through a surface binding group. An electric field is then applied to align the charged SWCNTs parallel to lengthwise directions of the plurality of trenches such that another end of the each of the SWCNTs binds to an adjacent metal anchor through another surface binding group. The aligned charged SWCNTs can be used as conducting channels for field effect transistors (FETs).

Abstract translation: 在形成布置成行和列的矩阵的多个金属锚定件和在衬底上分隔相邻的金属锚定排的多个沟槽之后，分散体包括在每个端部具有表面结合基团的带电荷的单壁碳纳米管（SWCNT） 带电的SWCNT被引导流过多个沟槽。 在流动过程中，每个带电的SWCNT的一端通过表面结合基团与相应的金属锚结合。 然后施加电场以使带电的SWCNT平行于多个沟槽的长度方向排列，使得每个SWCNT的另一端通过另一表面结合基团结合相邻的金属锚。 对准的带电SWCNT可用作场效应晶体管（FET）的导通通道。