公开(公告)号：US09559051B1

公开(公告)日：2017-01-31

申请号：US14976417

申请日：2015-12-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yongchun Xin ,  Jang H. Sim ,  Junjing Bao ,  Zhigang Song ,  Yunsheng Song

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/3205 ,  H01L21/3213 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/32055 ,  H01L21/32137 ,  H01L21/76804 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76879 ,  H01L23/53238 ,  H01L2221/1063

Abstract: A method for depositing a conductor in the via opening electronic structure removes the via bottom liner so that the conductor deposited in the via opening directly contacts the underlying conductive layer. The method includes depositing amorphous silicon over the dielectric layer and the liner layer on the via opening sidewalls and bottom. The amorphous silicon extends substantially over the entire via opening while leaving below a void within the via opening. The amorphous silicon over the via opening and on the via opening bottom and the liner layer on the via opening bottom are anisotropically etched to leave a layer of amorphous silicon over the dielectric layer and the via opening side walls. The amorphous silicon is then removed to form a via opening having a substantially open-bottom liner. The conductor is then deposited in the via opening and contacts the underlying conductive layer.

Abstract translation: 用于在通孔开口电子结构中沉积导体的方法去除了通孔底部衬垫，使得沉积在通孔开口中的导体直接接触下面的导电层。 该方法包括在通孔开口侧壁和底部上的绝缘层和衬垫层上沉积非晶硅。 非晶硅基本上在整个通孔开口上延伸，同时在通孔开口内留下空隙。 在通孔开口和通孔开口底部和通孔开口底部上的衬垫层上的非晶硅被各向异性地蚀刻，以在电介质层和通孔开口侧壁上留下一层非晶硅。 然后去除非晶硅以形成具有基本上开口底部衬垫的通孔。 然后将导体沉积在通孔开口中并接触下面的导电层。

公开(公告)号：US10109046B2

公开(公告)日：2018-10-23

申请号：US15213665

申请日：2016-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert Boyd Finlay ,  Yunsheng Song

IPC: G06T7/00 ,  G06T7/60 ,  G06K9/52 ,  G06K9/62 ,  G06T7/20

Abstract: Systems for and methods of detecting faults in semiconductor wafers are provided. One method includes, for instance: monitoring, with at least one sensor, a recipe for manufacturing a semiconductor wafer; tracking, with a fault detection system, a set of steps for the recipe; determining a start of a step; sensing a set of data related to at least one parameter of the step; generating, by an imaging system, an image of the set of data; displaying, on a display, the image of the set of data; calculating, by the fault detection system, a pixel area ratio from the image of the set of data; determining if a fault exists in the wafer based upon the pixel area ratio; and displaying, on the display, an indication of the fault during real-time and at an end of the step.

公开(公告)号：US09337334B2

公开(公告)日：2016-05-10

申请号：US14257395

申请日：2014-04-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hari V. Mallela ,  Edward J. Nowak ,  Yunsheng Song ,  Reinaldo A. Vega ,  Keith Kwong Hon Wong ,  Zhijian Yang

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/49 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L21/28 ,  H03K17/687 ,  H01L29/51

CPC classification number: H01L29/78391 ,  H01L21/28026 ,  H01L21/28291 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/49 ,  H01L29/516 ,  H01L29/66568 ,  H01L29/6684 ,  H03K17/687

Abstract: A semiconductor memory device including a channel region and a ferromagnetic gate is provided. The channel region can be formed within a semiconductor nanowire. The ferromagnetic gate is programmed with a selected orientation of magnetization by the electrical current that passes through the channel region in one direction or another. The orientation of the magnetization in the ferromagnetic gate can be detected by changes in the threshold voltage of a field effect transistor employing the ferromagnetic gate as a gate electrode, or can be detected by the resistance of the channel region that changes with the orientation of the magnetization in a two terminal device.

Abstract translation: 提供了包括沟道区和铁磁栅的半导体存储器件。 沟道区可以形成在半导体纳米线内。 铁磁栅极通过在一个方向上通过沟道区域的电流以选定的磁化取向来编程。 可以通过使用铁磁栅极作为栅电极的场效应晶体管的阈值电压的变化来检测铁磁栅极中的磁化方向，或者可以通过随着取向的变化而改变的沟道区域的电阻来检测 二端装置的磁化。