公开(公告)号：US20140282345A1

公开(公告)日：2014-09-18

申请号：US13838378

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei YUAN ,  Jongwook KYE ,  Harry LEVINSON

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A method and apparatus for insertion of a via improving a manufacturability of a resulting device while ensuring compliance with DRC rules are disclosed. Embodiments include: determining a layer of a substrate of an IC design having a first via and a plurality of routes, the plurality of routes extending horizontally on the substrate and placed on one of a plurality of equally spaced vertical positions; comparing a region of the layer extending vertically between a first set of the plurality of routes and extending horizontally between a second set of the plurality of the routes with one or more threshold values, the region being adjacent to the first via and being separated from the plurality of routes; and inserting a second via based on the comparison.

Abstract translation: 公开了一种用于插入通孔的方法和装置，其改善了所得到的装置的可制造性，同时确保符合DRC规则。 实施例包括：确定具有第一通孔和多个路线的IC设计的基板的层，所述多个路线在基板上水平延伸并且放置在多个等间隔的垂直位置中的一个上; 比较在多个路线的第一组之间垂直延伸并且在第二组多个路线之间水平延伸的层的区域与一个或多个阈值，所述区域与第一通孔相邻并且与第一通孔分离 多条路线; 以及基于所述比较来插入第二通孔。

公开(公告)号：US20180053757A1

公开(公告)日：2018-02-22

申请号：US15238107

申请日：2016-08-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei YUAN ,  Xuelian ZHU ,  Harry J. LEVINSON

IPC: H01L27/02 ,  H01L27/118 ,  H01L21/308 ,  H01L21/84 ,  H01L27/12 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5077 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/845 ,  H01L27/11803 ,  H01L27/1211

Abstract: A semiconductor structure includes a substrate having a plurality of semiconductor devices disposed therein. A dielectric layer is disposed over the substrate. A plurality of substantially parallel metal lines are disposed in the dielectric layer. The metal lines include active lines for routing signals to and from the devices, and dummy lines which do not route signals to and from the devices. Signal cuts are disposed in the active lines. The signal cuts define tips of the active lines. Assist cuts are disposed exclusively in the dummy lines and do not define tips of the active lines. The assist cuts are located proximate the signal cuts such that a first density of assist cuts and signal cuts in an area surrounding the signal cuts is substantially greater than a second density of signal cuts alone in the same area.

公开(公告)号：US20150220676A1

公开(公告)日：2015-08-06

申请号：US14687477

申请日：2015-04-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei YUAN ,  Soo Han CHOI ,  Li YANG ,  Jongwook KYE

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: Methodologies and an apparatus enabling a generation of color undeterminable polygons in IC designs are disclosed. Embodiments include: determining a plurality of first routes extending horizontally in an IC design, each of the plurality of first routes being placed on one of a plurality of equally spaced vertical positions of the IC design; determining whether a second route overlaps one of the vertical positions of the plurality of equally spaced vertical positions; and selecting a design rule for the second route based on the determination of whether the second route overlaps.