公开(公告)号：US20150067633A1

公开(公告)日：2015-03-05

申请号：US14017594

申请日：2013-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei YUAN ,  Soo Han CHOI ,  Li YANG ,  Jongwook KYE

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: Methodologies and an apparatus enabling a generation of color undeterminable polygons in IC designs are disclosed. Embodiments include: determining a plurality of first routes extending horizontally in an IC design, each of the plurality of first routes being placed on one of a plurality of equally spaced vertical positions of the IC design; determining whether a second route overlaps one of the vertical positions of the plurality of equally spaced vertical positions; and selecting a design rule for the second route based on the determination of whether the second route overlaps.

Abstract translation: 公开了在IC设计中能够产生颜色不可确定的多边形的方法和装置。 实施例包括：确定在IC设计中水平延伸的多个第一路线，所述多条第一路线中的​​每条路线被放置在所述IC设计的多个相等间隔的垂直位置之一上; 确定第二路线是否与所述多个等间隔垂直位置的垂直位置之一重叠; 以及基于所述第二路由是否重叠的确定来选择所述第二路由的设计规则。

公开(公告)号：US20160378906A1

公开(公告)日：2016-12-29

申请号：US15040235

申请日：2016-02-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei YUAN ,  Jongwook KYE ,  Harry J. LEVINSON

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  H01L21/027

Abstract: Methods for performing design rule checking of a circuit design are provided. The methods include, for instance: providing a circuit design for an integrated circuit layer, in which the circuit design includes a plurality of design lines oriented in a particular direction; and automatically performing a design rule check of the circuit design, which may include forming a verification pattern for the circuit design, the verification pattern comprising a plurality of verification lines and a plurality of verification regions, wherein one or more verification regions are associated with and connected to one verification line of the plurality of verification lines, and checking the verification pattern for any verification line overlapping a verification region. The circuit design may be considered to fail the design rule check if an end of one verification line overlaps any verification region associated with another verification line of the verification pattern.

Abstract translation: 提供了对电路设计进行设计规则检查的方法。 所述方法包括例如提供用于集成电路层的电路设计，其中电路设计包括沿特定方向定向的多个设计线; 并且自动执行电路设计的设计规则检查，其可以包括形成用于电路设计的验证模式，所述验证模式包括多个验证线和多个验证区域，其中一个或多个验证区域与 连接到多条验证线的一条验证线，并且检查与验证区域重叠的任何验证线的验证模式。 可以认为电路设计不能使设计规则检查一个验证线的末端是否与与验证图案的另一验证线相关联的任何验证区域重叠。

公开(公告)号：US20160293478A1

公开(公告)日：2016-10-06

申请号：US14679060

申请日：2015-04-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei YUAN ,  Jongwook KYE ,  Harry J. LEVINSON

IPC: H01L21/768 ,  H01L21/027 ,  H01L23/532 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257

Abstract: Self-aligned double patterning processes to produce metal route between and connecting conductive lines are disclosed. Embodiments include forming a hard mask over a dielectric layer; forming a patterning template including plural parallel linear elements on the hard mask, wherein said hard mask is exposed between adjacent parallel linear elements; forming a block mask covering a portion of said adjacent parallel linear elements and spaces therebetween; etching exposed portions of said hard mask through said block mask and said patterning template defining plural parallel lines; removing said block mask and said patterning template; forming a cut mask above said hard mask to define an opening perpendicular to and connecting two adjacent parallel lines; etching said hard mask through said cut mask and removing the cut mask; etching recesses in the dielectric layer through said hard mask; removing the hard mask; and filling said recesses with a conductive material.

Abstract translation: 公开了用于在导线之间产生金属路径的自对准双重图案化工艺。 实施例包括在电介质层上形成硬掩模; 在硬掩模上形成包括多个平行线形元件的图案化模板，其中所述硬掩模在相邻的平行线性元件之间露出; 形成覆盖所述相邻的平行线性元件的一部分和其间的空间的块掩模; 通过所述块掩模蚀刻所述硬掩模的暴露部分和限定多条平行线的所述图案化模板; 去除所述块掩模和所述图案化模板; 在所述硬掩模上形成切割掩模以限定垂直于并连接两个相邻平行线的开口; 通过所述切割掩模蚀刻所述硬掩模并除去切割的掩模; 通过所述硬掩模蚀刻介电层中的凹槽; 去除硬面膜; 并用导电材料填充所述凹部。

公开(公告)号：US20140346662A1

公开(公告)日：2014-11-27

申请号：US13902395

申请日：2013-05-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mahbub RASHED ,  Lei YUAN

IPC: G06F17/50 ,  H01L29/78 ,  H01L29/66

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785 ,  Y02T10/82

Abstract: Methods for accommodating a non-integer multiple of the M2 pitch for the cell height of a semiconductor cell and the resulting devices are disclosed. Embodiments may include forming a cell within an integrated circuit (IC) with a height of a first integer and a remainder times a track pitch of a metal track layer, and forming power rails within the metal track layer at boundaries of the cell accommodating for the remainder.

Abstract translation: 公开了用于容纳用于半导体单元的单元高度的M2间距的非整数倍的方法以及所得到的器件。 实施例可以包括在具有第一整数和余数乘以金属轨道层的轨道间距的集成电路（IC）内形成单元，以及在金属轨道层的边界处形成用于为 余。

公开(公告)号：US20140225270A1

公开(公告)日：2014-08-14

申请号：US13766141

申请日：2013-02-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei YUAN ,  Jongwook Kye ,  Harry Levinson

IPC: H01L21/308 ,  H01L23/50

CPC classification number: H01L23/49838 ,  H01L21/0337 ,  H01L21/308 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L23/50 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of the substrate being separated from the first mandrels and between two of the first spacers, each of the first mandrels, first non-mandrel regions, and first spacers having a width equal to a distance; and providing a second mandrel having a width of at least twice the distance and being separated from one of the first non-mandrel regions by a second spacer.

Abstract translation: 公开了一种用于有效的非轨道路由的方法以及所得到的设备。 实施例包括：在基板上提供硬掩模; 在硬掩模上提供多个第一心轴; 在每个所述第一心轴的每一侧上提供第一间隔件; 提供所述基板的多个第一非心轴区域与所述第一心轴分开并且在所述第一间隔件中的两个之间，所述第一心轴，第一非心轴区域和第一间隔件中的每一个具有等于一定距离的宽度; 以及提供具有至少两倍距离的宽度的第二心轴，并且通过第二间隔件与第一非心轴区域之一分离。

公开(公告)号：US20160117432A1

公开(公告)日：2016-04-28

申请号：US14523558

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei YUAN ,  Irene LIN ,  Jongwook KYE ,  Mahbub RASHED

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  Y02T10/82

Abstract: A method and apparatus for an assisted metal routing is disclosed. Embodiments may include: determining an initial block mask having a first inner vertex for forming a metal routing layer of an integrated circuit (IC); adding an assistant metal portion within the metal routing layer; and determining a modified block mask based on the assistant metal portion for forming the metal routing layer.

Abstract translation: 公开了一种用于辅助金属布线的方法和装置。 实施例可以包括：确定具有用于形成集成电路（IC）的金属布线层的第一内部顶点的初始块掩模; 在所述金属布线层内添加辅助金属部分; 以及基于用于形成金属布线层的辅助金属部分确定修改的块掩模。

公开(公告)号：US20150213184A1

公开(公告)日：2015-07-30

申请号：US14163511

申请日：2014-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei YUAN ,  Mahbub RASHED ,  Jongwook KYE

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  Y02T10/82

Abstract: A methodology for a modified cell architecture and the resulting devices are disclosed. Embodiments may include determining a first vertical track spacing for a plurality of first routes for an integrated circuit (IC) design, each of the plurality of first routes having a first width, determining a second vertical track spacing for a second route for the IC design, the second route having a second width, and designating a cell vertical dimension for the IC design based on the first and second vertical track spacings.

Abstract translation: 公开了修改的小区体系结构的方法以及所得到的设备。 实施例可以包括确定用于集成电路（IC）设计的多个第一路由的第一垂直轨道间隔，所述多个第一路线中的​​每一条路径具有第一宽度，确定用于IC设计的第二路线的第二垂直轨道间距 所述第二路径具有第二宽度，并且基于所述第一和第二垂直轨道间隔指定所述IC设计的单元垂直尺寸。

公开(公告)号：US20150287604A1

公开(公告)日：2015-10-08

申请号：US14246197

申请日：2014-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason E. STEPHENS ,  Lei YUAN ,  Lixia LEI ,  David PRITCHARD ,  Tuhin Guha NEOGI

IPC: H01L21/28

CPC classification number: H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0207

Abstract: A method is provided for fabricating cross-coupled line segments on a wafer for use, for instance, in fabricating cross-coupled gates of two or more transistors. The fabricating includes: patterning a first line segment with a first side projection using a first mask; and patterning a second line segment with a second side projection using a second mask. The second line segment is offset from the first line segment, and the patterned second side projection overlies the patterned first side projection, and facilitates defining a cross-stitch segment connecting the first and second line segments. The method further includes selectively cutting the first and second line segments in defining the cross-coupled line segments from the first and second line segments and the cross-stitch segment.

Abstract translation: 提供了一种用于在晶片上制造交叉耦合线段以用于例如制造两个或多个晶体管的交叉耦合栅极的方法。 该制造包括：使用第一掩模使具有第一侧面突起的第一线段图案化; 以及使用第二掩模用第二侧面突起构图第二线段。 第二线段与第一线段偏移，并且图案化的第二侧突起覆盖图案化的第一侧突起，并且有助于限定连接第一和第二线段的十字绣线段。 该方法还包括在限定来自第一和第二线段和十字绣段的交叉耦合线段时选择性地切割第一和第二线段。

公开(公告)号：US20150187702A1

公开(公告)日：2015-07-02

申请号：US14645598

申请日：2015-03-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mahbub RASHED ,  Yuansheng MA ,  Irene LIN ,  Jason STEPHENS ,  Yunfei DENG ,  Lei YUAN ,  Jongwook KYE ,  Rod AUGUR ,  Shibly AHMED ,  Subramani KENGERI ,  Suresh VENKATESAN

IPC: H01L23/538 ,  H01L27/092 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L23/5386 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/5384 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.

Abstract translation: 公开了一种使用扩散接触结构提供MOL构造的方法。 实施例包括：在衬底中提供第一扩散区域; 经由第一光刻工艺提供第一扩散接触结构; 经由第二光刻工艺提供第二扩散接触结构; 以及将所述第一扩散接触结构耦合到所述第一扩散区和所述第二扩散接触结构。 实施例包括：在衬底中提供第二扩散区域; 在所述第一和第二扩散区之间提供扩散间隙区域; 在所述扩散间隙区域上提供所述扩散接触结构; 以及经由扩散接触结构耦合第一和第二扩散区域。

公开(公告)号：US20150028489A1

公开(公告)日：2015-01-29

申请号：US14513834

申请日：2014-10-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei YUAN ,  Jongwook KYE ,  Harry LEVINSON

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49838 ,  H01L21/0337 ,  H01L21/308 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L23/50 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of the substrate being separated from the first mandrels and between two of the first spacers, each of the first mandrels, first non-mandrel regions, and first spacers having a width equal to a distance; and providing a second mandrel having a width of at least twice the distance and being separated from one of the first non-mandrel regions by a second spacer.

Abstract translation: 公开了一种用于有效的非轨道路由的方法以及所得到的设备。 实施例包括：在基板上提供硬掩模; 在硬掩模上提供多个第一心轴; 在每个所述第一心轴的每一侧上提供第一间隔件; 提供所述基板的多个第一非心轴区域与所述第一心轴分开并且在所述第一间隔件中的两个之间，所述第一心轴，第一非心轴区域和第一间隔件中的每一个具有等于一定距离的宽度; 以及提供具有至少两倍距离的宽度的第二心轴，并且通过第二间隔件与第一非心轴区域之一分离。