公开(公告)号：US20180053662A1

公开(公告)日：2018-02-22

申请号：US15238760

申请日：2016-08-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Jan PAWLAK ,  Harry J. LEVINSON

IPC: H01L21/308 ,  H01L21/306 ,  H01L29/04 ,  H01L21/02

CPC classification number: H01L21/0243 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02658 ,  H01L21/30608 ,  H01L21/3081

Abstract: A method of texturing a silicon (Si) wafer and the resulting device are provided. Embodiments include forming a mask over an upper surface of a Si wafer; patterning the mask by direct-self assembly (DSA); etching the Si wafer through the patterned mask to form holes in the Si wafer; removing the mask; and etching the holes to form a textured surface in the Si wafer.

公开(公告)号：US20180053757A1

公开(公告)日：2018-02-22

申请号：US15238107

申请日：2016-08-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei YUAN ,  Xuelian ZHU ,  Harry J. LEVINSON

IPC: H01L27/02 ,  H01L27/118 ,  H01L21/308 ,  H01L21/84 ,  H01L27/12 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5077 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/845 ,  H01L27/11803 ,  H01L27/1211

Abstract: A semiconductor structure includes a substrate having a plurality of semiconductor devices disposed therein. A dielectric layer is disposed over the substrate. A plurality of substantially parallel metal lines are disposed in the dielectric layer. The metal lines include active lines for routing signals to and from the devices, and dummy lines which do not route signals to and from the devices. Signal cuts are disposed in the active lines. The signal cuts define tips of the active lines. Assist cuts are disposed exclusively in the dummy lines and do not define tips of the active lines. The assist cuts are located proximate the signal cuts such that a first density of assist cuts and signal cuts in an area surrounding the signal cuts is substantially greater than a second density of signal cuts alone in the same area.

公开(公告)号：US20160378906A1

公开(公告)日：2016-12-29

申请号：US15040235

申请日：2016-02-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei YUAN ,  Jongwook KYE ,  Harry J. LEVINSON

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  H01L21/027

Abstract: Methods for performing design rule checking of a circuit design are provided. The methods include, for instance: providing a circuit design for an integrated circuit layer, in which the circuit design includes a plurality of design lines oriented in a particular direction; and automatically performing a design rule check of the circuit design, which may include forming a verification pattern for the circuit design, the verification pattern comprising a plurality of verification lines and a plurality of verification regions, wherein one or more verification regions are associated with and connected to one verification line of the plurality of verification lines, and checking the verification pattern for any verification line overlapping a verification region. The circuit design may be considered to fail the design rule check if an end of one verification line overlaps any verification region associated with another verification line of the verification pattern.

Abstract translation: 提供了对电路设计进行设计规则检查的方法。 所述方法包括例如提供用于集成电路层的电路设计，其中电路设计包括沿特定方向定向的多个设计线; 并且自动执行电路设计的设计规则检查，其可以包括形成用于电路设计的验证模式，所述验证模式包括多个验证线和多个验证区域，其中一个或多个验证区域与 连接到多条验证线的一条验证线，并且检查与验证区域重叠的任何验证线的验证模式。 可以认为电路设计不能使设计规则检查一个验证线的末端是否与与验证图案的另一验证线相关联的任何验证区域重叠。

公开(公告)号：US20160293478A1

公开(公告)日：2016-10-06

申请号：US14679060

申请日：2015-04-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei YUAN ,  Jongwook KYE ,  Harry J. LEVINSON

IPC: H01L21/768 ,  H01L21/027 ,  H01L23/532 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257

Abstract: Self-aligned double patterning processes to produce metal route between and connecting conductive lines are disclosed. Embodiments include forming a hard mask over a dielectric layer; forming a patterning template including plural parallel linear elements on the hard mask, wherein said hard mask is exposed between adjacent parallel linear elements; forming a block mask covering a portion of said adjacent parallel linear elements and spaces therebetween; etching exposed portions of said hard mask through said block mask and said patterning template defining plural parallel lines; removing said block mask and said patterning template; forming a cut mask above said hard mask to define an opening perpendicular to and connecting two adjacent parallel lines; etching said hard mask through said cut mask and removing the cut mask; etching recesses in the dielectric layer through said hard mask; removing the hard mask; and filling said recesses with a conductive material.

Abstract translation: 公开了用于在导线之间产生金属路径的自对准双重图案化工艺。 实施例包括在电介质层上形成硬掩模; 在硬掩模上形成包括多个平行线形元件的图案化模板，其中所述硬掩模在相邻的平行线性元件之间露出; 形成覆盖所述相邻的平行线性元件的一部分和其间的空间的块掩模; 通过所述块掩模蚀刻所述硬掩模的暴露部分和限定多条平行线的所述图案化模板; 去除所述块掩模和所述图案化模板; 在所述硬掩模上形成切割掩模以限定垂直于并连接两个相邻平行线的开口; 通过所述切割掩模蚀刻所述硬掩模并除去切割的掩模; 通过所述硬掩模蚀刻介电层中的凹槽; 去除硬面膜; 并用导电材料填充所述凹部。