公开(公告)号：US20170018573A1

公开(公告)日：2017-01-19

申请号：US14801519

申请日：2015-07-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Manfred ELLER

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L29/66553 ,  H01L29/66772 ,  H01L29/78648

Abstract: A semiconductor device includes a semiconductor substrate, an insulating layer on a top surface of the substrate, and a first semiconductor transistor on the insulating layer, the transistor including an active region with a source region, a drain region, a channel region between the source and drain regions and a gate structure over the channel region, the gate structure extending beyond the transistor to an adjacent area. An outer well is included in the substrate, an inner well of an opposite type as the outer well situated within the outer well and under the active region and adjacent area, and a contact for the inner well in the adjacent area, the contact surrounding the gate structure. Operating the device includes applying a variable voltage at the contact for the inner well, a threshold voltage for the first transistor being altered by the variable voltage. The inner well and gate may be exposed and contacts created therefor together.

Abstract translation: 半导体器件包括半导体衬底，衬底顶表面上的绝缘层和绝缘层上的第一半导体晶体管，晶体管包括有源区，源区，漏区，源极之间的沟道区 漏极区和沟道区上的栅极结构，栅极结构延伸超过晶体管到相邻区域。 外部孔包括在衬底中，与外部阱中位于外部阱内并且在有源区域和相邻区域下方的相反类型的内部阱以及相邻区域中的内部阱的接触，围绕 门结构。 操作器件包括在内部阱的触点处施加可变电压，第一晶体管的阈值电压被可变电压改变。 内部井和闸门可能被暴露，并且一起形成了与之相联系的接触。

公开(公告)号：US20150243652A1

公开(公告)日：2015-08-27

申请号：US14188898

申请日：2014-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Manoj JOSHI ,  Manfred ELLER ,  Rohit PAL ,  Richard J. CARTER ,  Srikanth Balaji SAMAVEDAM ,  Bongki LEE ,  Jin Ping LIU

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L21/823842 ,  H01L21/82345 ,  H01L27/088 ,  H01L27/092

Abstract: In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage.

Abstract translation: 在一个方面，这里阐述了具有形成在衬底结构中的第一场效应晶体管和形成在衬底结构中的第二场效应晶体管的半导体器件。 第一场效应晶体管可以包括第一衬底结构掺杂，第一栅叠层和第一阈值电压。 第二场效应晶体管可以包括第一衬底结构掺杂，不同于第一栅极叠层的第二栅极堆叠以及不同于第一阈值电压的第二阈值电压。

公开(公告)号：US20150243563A1

公开(公告)日：2015-08-27

申请号：US14189085

申请日：2014-02-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bongki LEE ,  Jin Ping LIU ,  Manoj JOSHI ,  Manfred ELLER ,  Rohit PAL ,  Richard J. CARTER ,  Srikanth Balaji SAMAVEDAM

IPC: H01L21/8234 ,  H01L29/49 ,  H01L21/28 ,  H01L27/088

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

Abstract: In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack.

Abstract translation: 在一个方面，这里提出了具有第一多个场效应晶体管和第二多个场效应晶体管的集成电路，其中第一多个场效应晶体管的场效应晶体管各自具有第一栅极堆叠，并且其中场效应 第二多个场效应晶体管的晶体管每个都具有第二栅极堆叠，第二栅极堆叠通过具有与第一栅极堆叠共同的金属层与第一栅极堆叠而不同于第一栅极堆叠，第二栅极堆叠包括第一栅极堆叠的第一厚度 第一栅极堆叠和第二栅极堆叠处的第二厚度。