公开(公告)号：US20180233415A1

公开(公告)日：2018-08-16

申请号：US15947479

申请日：2018-04-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani PANDEY ,  Baofu ZHU ,  Srikanth Balaji SAMAVEDAM

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/66818 ,  H01L29/7853

Abstract: A method for producing a finFET having a fin with thinned sidewalls on a lower portion above a shallow trench isolation (STI) regions is provided. Embodiments include forming a fin surrounded by STI regions on a substrate; recessing the STI regions, revealing an upper portion of the fin; forming a spacer over side and upper surfaces of the upper portion of the fin; recessing the STI regions, exposing a lower portion of the fin; and thinning sidewalls of the lower portion of the fin.

公开(公告)号：US20180040516A1

公开(公告)日：2018-02-08

申请号：US15229431

申请日：2016-08-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani PANDEY ,  Baofu ZHU ,  Srikanth Balaji SAMAVEDAM

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/66818 ,  H01L29/7853

Abstract: A method for producing a finFET having a fin with thinned sidewalls on a lower portion above a shallow trench isolation (STI) regions is provided. Embodiments include forming a fin surrounded by STI regions on a substrate; recessing the STI regions, revealing an upper portion of the fin; forming a spacer over side and upper surfaces of the upper portion of the fin; recessing the STI regions, exposing a lower portion of the fin; and thinning sidewalls of the lower portion of the fin.

公开(公告)号：US20150243658A1

公开(公告)日：2015-08-27

申请号：US14188778

申请日：2014-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Manoj JOSHI ,  Manfred ELLER ,  Richard J. CARTER ,  Srikanth Balaji SAMAVEDAM

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0922 ,  H01L27/0924

Abstract: Integrated circuits and fabrication methods are provided. The integrated circuit includes: a varying gate structure disposed over a substrate structure, the varying gate structure including a first gate stack in a first region of the substrate structure, and a second gate stack in a second region of the substrate structure; a first field-effect transistor in the first region, the first field-effect transistor including the first gate stack and having a first threshold voltage; and a second field-effect transistor in the second region, the second field-effect transistor including the second gate stack and having a second threshold voltage, where the first threshold voltage is different from the second threshold voltage. The methods include providing the varying gate structure, the providing including: sizing layer(s) of the varying gate structure with different thickness(es) in different region(s).

Abstract translation: 提供集成电路和制造方法。 集成电路包括：设置在衬底结构上的变化的栅极结构，所述变化的栅极结构包括在衬底结构的第一区域中的第一栅极堆叠，以及在衬底结构的第二区域中的第二栅极堆叠; 所述第一区域中的第一场效应晶体管，所述第一场效应晶体管包括所述第一栅极叠层并具有第一阈值电压; 以及第二区域中的第二场效应晶体管，所述第二场效应晶体管包括所述第二栅极堆叠并且具有第二阈值电压，其中所述第一阈值电压不同于所述第二阈值电压。 所述方法包括提供变化的栅极结构，所述提供包括：具有不同厚度（es）的不同栅极结构的尺寸层。

公开(公告)号：US20180337033A1

公开(公告)日：2018-11-22

申请号：US15596437

申请日：2017-05-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani PANDEY ,  Srikanth Balaji SAMAVEDAM ,  Jui-Hsuan FENG

IPC: H01L21/02

CPC classification number: H01L21/0243 ,  H01L21/02019 ,  H01L21/02381 ,  H01L21/02403 ,  H01L21/02518 ,  H01L21/02658 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/7856

Abstract: Devices and methods of fabricating devices are provided. One method includes: patterning an isolation gate disposed above a trench, the trench extending into a substrate; patterning a gate structure disposed above the substrate and adjacent the isolation gate; depositing a set of sidewall spacers on either side of the isolation gate and gate structure; etching a set of cavities between the isolation gate and gate structure and extending into the substrate; and epitaxially growing a set of epitaxial growths in the set of cavities, wherein the isolation gate is wider than the gate structure, and wherein epitaxial growths adjacent the isolation gate substantially conform to an oxide layer between the isolation gate and the trench, contacting at least a portion of a bottom surface and at least a portion of a side surface of the oxide layer.

公开(公告)号：US20160118414A1

公开(公告)日：2016-04-28

申请号：US14525842

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar SINGH ,  Srikanth Balaji SAMAVEDAM

IPC: H01L27/12 ,  H01L21/762 ,  H01L27/092 ,  H01L29/06 ,  H01L23/66 ,  H01L21/84 ,  H01L21/3105

CPC classification number: H01L27/1211 ,  H01L21/76229 ,  H01L21/7624 ,  H01L21/845 ,  H01L23/66 ,  H01L27/092 ,  H01L27/1207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Co-fabrication of a radio-frequency (RF) semiconductor device with a three-dimensional semiconductor device includes providing a starting three-dimensional semiconductor structure, the starting structure including a bulk silicon semiconductor substrate, raised semiconductor structure(s) coupled to the substrate and surrounded by a layer of isolation material. Span(s) of the layer of isolation material between adjacent raised structures are recessed, and a layer of epitaxial semiconductor material is created over the recessed span(s) of isolation material over which another layer of isolation material is created. The RF device(s) are fabricated on the layer of isolation material above the epitaxial material, which creates a local silicon-on-insulator, while the three-dimensional semiconductor device(s) can be fabricated on the raised structure(s).

Abstract translation: 具有三维半导体器件的射频（RF）半导体器件的共同制造包括提供起始三维半导体结构，起始结构包括体硅半导体衬底，耦合到衬底的凸起半导体结构 并被一层隔离材料包围。 在相邻的凸起结构之间的隔离材料层的跨度是凹进的，并且在隔离材料的凹陷跨度上形成一层外延半导体材料，在其上产生另一层隔离材料。 RF器件制造在外延材料上方的隔离材料层上，其产生局部绝缘体上硅，而三维半导体器件可以在凸起结构上制造。

公开(公告)号：US20150243652A1

公开(公告)日：2015-08-27

申请号：US14188898

申请日：2014-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Manoj JOSHI ,  Manfred ELLER ,  Rohit PAL ,  Richard J. CARTER ,  Srikanth Balaji SAMAVEDAM ,  Bongki LEE ,  Jin Ping LIU

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L21/823842 ,  H01L21/82345 ,  H01L27/088 ,  H01L27/092

Abstract: In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage.

Abstract translation: 在一个方面，这里阐述了具有形成在衬底结构中的第一场效应晶体管和形成在衬底结构中的第二场效应晶体管的半导体器件。 第一场效应晶体管可以包括第一衬底结构掺杂，第一栅叠层和第一阈值电压。 第二场效应晶体管可以包括第一衬底结构掺杂，不同于第一栅极叠层的第二栅极堆叠以及不同于第一阈值电压的第二阈值电压。

公开(公告)号：US20150243563A1

公开(公告)日：2015-08-27

申请号：US14189085

申请日：2014-02-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bongki LEE ,  Jin Ping LIU ,  Manoj JOSHI ,  Manfred ELLER ,  Rohit PAL ,  Richard J. CARTER ,  Srikanth Balaji SAMAVEDAM

IPC: H01L21/8234 ,  H01L29/49 ,  H01L21/28 ,  H01L27/088

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

Abstract: In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack.

Abstract translation: 在一个方面，这里提出了具有第一多个场效应晶体管和第二多个场效应晶体管的集成电路，其中第一多个场效应晶体管的场效应晶体管各自具有第一栅极堆叠，并且其中场效应 第二多个场效应晶体管的晶体管每个都具有第二栅极堆叠，第二栅极堆叠通过具有与第一栅极堆叠共同的金属层与第一栅极堆叠而不同于第一栅极堆叠，第二栅极堆叠包括第一栅极堆叠的第一厚度 第一栅极堆叠和第二栅极堆叠处的第二厚度。