公开(公告)号：US20150140756A1

公开(公告)日：2015-05-21

申请号：US14084756

申请日：2013-11-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hong YU ,  Seong Yeol MUN ,  Bingwu LIU ,  Lun ZHAO ,  Richard J. CARTER ,  Manfred ELLER

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: Circuit fabrication methods are provided which include, for example: providing one or more gate structures disposed over a substrate structure, the substrate structure including a first region and a second region; forming a plurality of U-shaped cavities extending into the substrate structure in the first region and the second region thereof, where at least one first cavity of the plurality of U-shaped cavities is disposed adjacent in one gate structure in the first region; and expanding the at least one first cavity further into the substrate structure to at least partially undercut the one gate structure, without expanding at least one second cavity of the plurality of U-shaped cavities, where forming the plurality of U-shaped cavities facilitates fabricating the circuit structure. In one embodiment, the circuit structure includes first and second transistors, having different device architectures, the first transistor having a higher mobility characteristic than the second transistor.

Abstract translation: 提供了电路制造方法，其包括例如：提供设置在衬底结构上方的一个或多个栅极结构，所述衬底结构包括第一区域和第二区域; 在所述第一区域和所述第二区域中形成延伸到所述衬底结构中的多个U形空腔，其中所述多个U形空腔中的至少一个第一空腔邻近所述第一区域中的一个栅极结构设置; 以及将所述至少一个第一空腔进一步扩展到所述衬底结构中以至少部分地切割所述一个栅极结构，而不扩展所述多个U形空腔中的至少一个第二空腔，其中形成所述多个U形空腔有助于制造 电路结构。 在一个实施例中，电路结构包括具有不同器件结构的第一和第二晶体管，第一晶体管具有比第二晶体管更高的迁移率特性。

公开(公告)号：US20150140751A1

公开(公告)日：2015-05-21

申请号：US14085906

申请日：2013-11-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong YU ,  Huang LIU ,  Lun ZHAO ,  Richard J. CARTER

IPC: H01L21/8238

CPC classification number: H01L21/823857 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/76829 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: Circuit fabrication methods are provided which include, for example: providing the circuit structure with at least one gate structure extending over a first region and a second region of a substrate structure, the at least one gate structure including a capping layer; and modifying an etch property of at least a portion of the capping layer of the at least one gate structure, where the modified etch property inhibits etching of the at least one gate structure during a first etch process facilitating fabrication of at least one first transistor in the first region and inhibits etching of the at least one gate structure during a second etch process facilitating fabrication of at least one second transistor in the second region.

Abstract translation: 提供了电路制造方法，其包括例如：为电路结构提供在衬底结构的第一区域和第二区域上延伸的至少一个栅极结构，所述至少一个栅极结构包括封盖层; 以及修改所述至少一个栅极结构的覆盖层的至少一部分的蚀刻特性，其中所述修改的蚀刻性能在第一蚀刻工艺期间禁止蚀刻所述至少一个栅极结构，促进制造至少一个第一晶体管 所述第一区域并且在第二蚀刻工艺期间抑制所述至少一个栅极结构的蚀刻，促进在所述第二区域中制造至少一个第二晶体管。

公开(公告)号：US20150243652A1

公开(公告)日：2015-08-27

申请号：US14188898

申请日：2014-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Manoj JOSHI ,  Manfred ELLER ,  Rohit PAL ,  Richard J. CARTER ,  Srikanth Balaji SAMAVEDAM ,  Bongki LEE ,  Jin Ping LIU

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L21/823842 ,  H01L21/82345 ,  H01L27/088 ,  H01L27/092

Abstract: In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage.

Abstract translation: 在一个方面，这里阐述了具有形成在衬底结构中的第一场效应晶体管和形成在衬底结构中的第二场效应晶体管的半导体器件。 第一场效应晶体管可以包括第一衬底结构掺杂，第一栅叠层和第一阈值电压。 第二场效应晶体管可以包括第一衬底结构掺杂，不同于第一栅极叠层的第二栅极堆叠以及不同于第一阈值电压的第二阈值电压。

公开(公告)号：US20150243563A1

公开(公告)日：2015-08-27

申请号：US14189085

申请日：2014-02-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bongki LEE ,  Jin Ping LIU ,  Manoj JOSHI ,  Manfred ELLER ,  Rohit PAL ,  Richard J. CARTER ,  Srikanth Balaji SAMAVEDAM

IPC: H01L21/8234 ,  H01L29/49 ,  H01L21/28 ,  H01L27/088

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

Abstract: In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack.

Abstract translation: 在一个方面，这里提出了具有第一多个场效应晶体管和第二多个场效应晶体管的集成电路，其中第一多个场效应晶体管的场效应晶体管各自具有第一栅极堆叠，并且其中场效应 第二多个场效应晶体管的晶体管每个都具有第二栅极堆叠，第二栅极堆叠通过具有与第一栅极堆叠共同的金属层与第一栅极堆叠而不同于第一栅极堆叠，第二栅极堆叠包括第一栅极堆叠的第一厚度 第一栅极堆叠和第二栅极堆叠处的第二厚度。

公开(公告)号：US20150287595A1

公开(公告)日：2015-10-08

申请号：US14725430

申请日：2015-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy WEI ,  Mariappan HARIHARAPUTHIRAN ,  Dae Geun YANG ,  Dae-Han CHOI ,  Xiang HU ,  Richard J. CARTER ,  Akshey SEHGAL

IPC: H01L21/033 ,  H01L29/78 ,  H01L21/027

CPC classification number: H01L21/0332 ,  G03F1/50 ,  H01L21/0276 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/823821 ,  H01L29/785

Abstract: Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.

Abstract translation: 提供了用于以紧密翅片间距形成翅片的半导体器件的装置和方法。 一种方法包括，例如：获得中间半导体器件; 在衬底上生长表层; 在外延层下方形成掺杂层; 在外延层上沉积第一氧化物层; 在第一氧化物层上施加电介质材料; 以及在介电材料上沉积光刻叠层。 一个中间半导体器件包括例如：具有至少一个n阱区和至少一个p阱区的衬底; 衬底上的掺杂层; 掺杂层上的外延层; 在epi层上的第一氧化物层; 第一氧化物层上的介电层; 以及介电层上的光刻叠层。

公开(公告)号：US20150243658A1

公开(公告)日：2015-08-27

申请号：US14188778

申请日：2014-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Manoj JOSHI ,  Manfred ELLER ,  Richard J. CARTER ,  Srikanth Balaji SAMAVEDAM

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0922 ,  H01L27/0924

Abstract: Integrated circuits and fabrication methods are provided. The integrated circuit includes: a varying gate structure disposed over a substrate structure, the varying gate structure including a first gate stack in a first region of the substrate structure, and a second gate stack in a second region of the substrate structure; a first field-effect transistor in the first region, the first field-effect transistor including the first gate stack and having a first threshold voltage; and a second field-effect transistor in the second region, the second field-effect transistor including the second gate stack and having a second threshold voltage, where the first threshold voltage is different from the second threshold voltage. The methods include providing the varying gate structure, the providing including: sizing layer(s) of the varying gate structure with different thickness(es) in different region(s).

Abstract translation: 提供集成电路和制造方法。 集成电路包括：设置在衬底结构上的变化的栅极结构，所述变化的栅极结构包括在衬底结构的第一区域中的第一栅极堆叠，以及在衬底结构的第二区域中的第二栅极堆叠; 所述第一区域中的第一场效应晶体管，所述第一场效应晶体管包括所述第一栅极叠层并具有第一阈值电压; 以及第二区域中的第二场效应晶体管，所述第二场效应晶体管包括所述第二栅极堆叠并且具有第二阈值电压，其中所述第一阈值电压不同于所述第二阈值电压。 所述方法包括提供变化的栅极结构，所述提供包括：具有不同厚度（es）的不同栅极结构的尺寸层。

公开(公告)号：US20150115418A1

公开(公告)日：2015-04-30

申请号：US14064840

申请日：2013-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy WEI ,  Mariappan HARIHARAPUTHIRAN ,  Dae Geun YANG ,  Dae-Han CHOI ,  Xiang HU ,  Richard J. CARTER ,  Akshey SEHGAL

IPC: H01L21/033 ,  G03F1/50

CPC classification number: H01L21/0332 ,  G03F1/50 ,  H01L21/0276 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/823821 ,  H01L29/785

Abstract: Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.