公开(公告)号：US20150084131A1

公开(公告)日：2015-03-26

申请号：US14032740

申请日：2013-09-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tsung-Liang CHEN ,  Hung-Wei LIU ,  Rohit PAL ,  Hsin-Neng TAI ,  Huey-Ming WANG ,  Tae Hoon LEE ,  Songkram SRIVATHANAKUL ,  Danni CHEN

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/42364 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092

Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.

公开(公告)号：US20180130712A1

公开(公告)日：2018-05-10

申请号：US15839243

申请日：2017-12-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan SPORER ,  Rohit PAL ,  Jeremy WAHL

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/092 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/6653 ,  H01L29/66795

Abstract: Methods for forming fins with a straight profile by preventing fin bending during STI fill and annealing are disclosed. Embodiments include providing STI regions separated by Si regions, each topped with a hardmask; planarizing the STI regions; removing the hardmask over a portion of the Si regions, forming recesses; forming a conformal spacer layer over the STI regions and in the recesses; removing horizontal portions of the spacer layer; epitaxially growing Si in each recess, forming fins; and etching the STI regions and a remainder of the spacer layer down to the Si regions to reveal the fins.

公开(公告)号：US20150380409A1

公开(公告)日：2015-12-31

申请号：US14315885

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mitsuhiro TOGO ,  Changyong XIAO ,  Yiqun LIU ,  Dina H. TRIYOSO ,  Rohit PAL

IPC: H01L27/092 ,  H01L21/321 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/324

CPC classification number: H01L27/0922 ,  H01L21/26513 ,  H01L21/32115 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/66795

Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

Abstract translation: 三个p型器件和在同一衬底上共同制造的三个n型器件提供了一个最低，低和规则阈值电压范围。 对于p型器件，使用栅极结构中的p型功函数金属的附加厚层并对其进行氧化来实现最低的范围，低Vt由厚的p型功函数金属单独实现 ，并且通过p型功函数金属的较薄层实现常规Vt。 对于n型器件，最低的Vt是通过用砷，氩，硅或锗注入氮化钽而不是在栅极结构中添加任何附加的p型功函数金属来实现的，低Vt是通过不添加 额外的p型功函数金属，而常规Vt是用最薄层的p型功函金属实现的。

公开(公告)号：US20150270364A1

公开(公告)日：2015-09-24

申请号：US14730887

申请日：2015-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tsung-Liang CHEN ,  Hung-Wei LIU ,  Rohit PAL ,  Hsin-Neng TAI ,  Huey-Ming WANG ,  Tae Hoon LEE ,  Songkram SRIVATHANAKUL ,  Danni CHEN

IPC: H01L29/423 ,  H01L27/092

CPC classification number: H01L29/42364 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092

Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.

Abstract translation: 提供了通过控制由这些方法形成的介电材料和半导体器件的凹陷来促进栅极高度均匀性的方法。 所述方法包括例如用n型晶体管和p型晶体管形成半导体器件的晶体管，n型晶体管和p型晶体管包括多个牺牲栅极结构和在上表面处的保护掩模 的多个牺牲栅极结构; 在多个牺牲栅极结构之上和之间提供电介质材料; 部分致密化介电材料以形成部分致密化的电介质材料; 进一步致密化部分致密化的介电材料以产生改性的介电材料; 以及在改性介电材料上形成基本平坦的表面，以控制电介质材料凹陷和栅极高度。

公开(公告)号：US20160049400A1

公开(公告)日：2016-02-18

申请号：US14924486

申请日：2015-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mitsuhiro TOGO ,  Changyong XIAO ,  Yiqun LIU ,  Dina H. TRIYOSO ,  Rohit PAL

IPC: H01L27/092

CPC classification number: H01L27/0922 ,  H01L21/26513 ,  H01L21/32115 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/66795

Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

公开(公告)号：US20150311083A1

公开(公告)日：2015-10-29

申请号：US14259497

申请日：2014-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Changyong XIAO ,  Hoong Shing WONG ,  Deepasree KONDUPARTHI ,  Rohit PAL

IPC: H01L21/28

CPC classification number: H01L29/6653 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7842

Abstract: A method includes providing a gate structure having a dummy gate, a first spacer along a side of the gate. The dummy gate and the spacer are removed to expose a gate dielectric. A second spacer is deposited on at least one side of a gate structure cavity and a top of the gate dielectric. A bottom portion of the second spacer is removed to expose the gate dielectric and the gate structure is wet cleaned.

Abstract translation: 一种方法包括提供具有虚拟栅极的栅极结构，沿栅极侧面的第一间隔物。 去除虚拟栅极和间隔物以露出栅极电介质。 第二间隔物沉积在栅极结构腔的至少一侧和栅极电介质的顶部。 去除第二间隔件的底部以暴露栅极电介质，并且将栅极结构湿式清洁。

公开(公告)号：US20150243652A1

公开(公告)日：2015-08-27

申请号：US14188898

申请日：2014-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Manoj JOSHI ,  Manfred ELLER ,  Rohit PAL ,  Richard J. CARTER ,  Srikanth Balaji SAMAVEDAM ,  Bongki LEE ,  Jin Ping LIU

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L21/823842 ,  H01L21/82345 ,  H01L27/088 ,  H01L27/092

Abstract: In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage.

Abstract translation: 在一个方面，这里阐述了具有形成在衬底结构中的第一场效应晶体管和形成在衬底结构中的第二场效应晶体管的半导体器件。 第一场效应晶体管可以包括第一衬底结构掺杂，第一栅叠层和第一阈值电压。 第二场效应晶体管可以包括第一衬底结构掺杂，不同于第一栅极叠层的第二栅极堆叠以及不同于第一阈值电压的第二阈值电压。

公开(公告)号：US20150243563A1

公开(公告)日：2015-08-27

申请号：US14189085

申请日：2014-02-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bongki LEE ,  Jin Ping LIU ,  Manoj JOSHI ,  Manfred ELLER ,  Rohit PAL ,  Richard J. CARTER ,  Srikanth Balaji SAMAVEDAM

IPC: H01L21/8234 ,  H01L29/49 ,  H01L21/28 ,  H01L27/088

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

Abstract: In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack.

Abstract translation: 在一个方面，这里提出了具有第一多个场效应晶体管和第二多个场效应晶体管的集成电路，其中第一多个场效应晶体管的场效应晶体管各自具有第一栅极堆叠，并且其中场效应 第二多个场效应晶体管的晶体管每个都具有第二栅极堆叠，第二栅极堆叠通过具有与第一栅极堆叠共同的金属层与第一栅极堆叠而不同于第一栅极堆叠，第二栅极堆叠包括第一栅极堆叠的第一厚度 第一栅极堆叠和第二栅极堆叠处的第二厚度。