公开(公告)号：US10164099B2

公开(公告)日：2018-12-25

申请号：US15889367

申请日：2018-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani Pandey ,  Pei Zhao ,  Baofu Zhu ,  Francis L. Benistant

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66

Abstract: One illustrative device disclosed herein includes, among other things, a fin defined on a substrate. A gate electrode structure is positioned above the fin in a channel region. A source/drain region is defined in the fin. The source/drain region includes a first epitaxial semiconductor material. The first epitaxial semiconductor material includes a dopant species having a first concentration. A diffusion blocking layer is positioned above the first epitaxial semiconductor material. A second epitaxial semiconductor material is positioned above the diffusion blocking layer. The second epitaxial semiconductor material includes the dopant species having a second concentration greater than the first concentration.

公开(公告)号：US10020386B1

公开(公告)日：2018-07-10

申请号：US15454511

申请日：2017-03-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jagar Singh ,  Baofu Zhu

IPC: H01L29/735 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/735 ,  H01L27/0259 ,  H01L29/0623 ,  H01L29/0646 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/1008 ,  H01L29/107

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage, analog bipolar devices and methods of manufacture. The structure includes: a base region formed in a substrate; a collector region formed in the substrate and comprising a deep n-well region and an n-well region; and an emitter region formed in the substrate and comprising a deep n-well region and an n-well region.

公开(公告)号：US20180175198A1

公开(公告)日：2018-06-21

申请号：US15889367

申请日：2018-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani Pandey ,  Pei Zhao ,  Baofu Zhu ,  Francis L. Benistant

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L29/16

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: One illustrative device disclosed herein includes, among other things, a fin defined on a substrate. A gate electrode structure is positioned above the fin in a channel region. A source/drain region is defined in the fin. The source/drain region includes a first epitaxial semiconductor material. The first epitaxial semiconductor material includes a dopant species having a first concentration. A diffusion blocking layer is positioned above the first epitaxial semiconductor material. A second epitaxial semiconductor material is positioned above the diffusion blocking layer. The second epitaxial semiconductor material includes the dopant species having a second concentration greater than the first concentration.

公开(公告)号：US09966313B2

公开(公告)日：2018-05-08

申请号：US15229431

申请日：2016-08-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani Pandey ,  Baofu Zhu ,  Srikanth Balaji Samavedam

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/66818 ,  H01L29/7853

Abstract: A method for producing a finFET having a fin with thinned sidewalls on a lower portion above a shallow trench isolation (STI) regions is provided. Embodiments include forming a fin surrounded by STI regions on a substrate; recessing the STI regions, revealing an upper portion of the fin; forming a spacer over side and upper surfaces of the upper portion of the fin; recessing the STI regions, exposing a lower portion of the fin; and thinning sidewalls of the lower portion of the fin.

公开(公告)号：US20170229578A1

公开(公告)日：2017-08-10

申请号：US15019273

申请日：2016-02-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani Pandey ,  Pei Zhao ,  Baofu Zhu ,  Francis L. Benistant

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/08 ,  H01L29/16

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming a gate electrode structure above a channel region defined in a semiconductor material. The semiconductor material is recessed in a source/drain region. A first material is epitaxially grown in the source/drain region. The first material includes a dopant species having a first concentration. A diffusion blocking layer is formed in the source/drain region above the first material. A second material is epitaxially grown in the source/drain region above the diffusion blocking layer. The second material comprises the dopant species having a second concentration greater than the first concentration.