公开(公告)号：US09947788B2

公开(公告)日：2018-04-17

申请号：US15019273

申请日：2016-02-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani Pandey ,  Pei Zhao ,  Baofu Zhu ,  Francis L. Benistant

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming a gate electrode structure above a channel region defined in a semiconductor material. The semiconductor material is recessed in a source/drain region. A first material is epitaxially grown in the source/drain region. The first material includes a dopant species having a first concentration. A diffusion blocking layer is formed in the source/drain region above the first material. A second material is epitaxially grown in the source/drain region above the diffusion blocking layer. The second material comprises the dopant species having a second concentration greater than the first concentration.

公开(公告)号：US20170309623A1

公开(公告)日：2017-10-26

申请号：US15135358

申请日：2016-04-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shesh Mani Pandey ,  Baofu Zhu

IPC: H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/67

CPC classification number: H01L27/0886 ,  H01L21/67155 ,  H01L21/823431 ,  H01L29/1037 ,  H01L29/66818 ,  H01L29/7853

Abstract: We disclose semiconductor devices, comprising a semiconductor substrate comprising bulk silicon; and a plurality of fins formed on the semiconductor substrate; wherein each of the plurality of fins comprises a lower portion disposed on the semiconductor substrate and having a first width, and an upper portion disposed on the lower portion and having a second width, wherein the second width is greater than the first width, as well as methods, apparatus, and systems for fabricating such semiconductor devices.

公开(公告)号：US08846464B1

公开(公告)日：2014-09-30

申请号：US13799814

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bingwu Liu ,  Baofu Zhu ,  Nam Sung Kim

IPC: H01L21/338 ,  H01L29/66

CPC classification number: H01L29/66545 ,  H01L21/28123 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78

Abstract: An approach for controlling a critical dimension (CD) of a RMG of a semiconductor device is provided. Specifically, embodiments of the present invention allow for CD consistency between a dummy gate and a subsequent RMG. In a typical embodiment, a dummy gate having a cap layer is formed over a substrate. A re-oxide layer is then formed over the substrate and around the dummy gate. A set of doping implants will then be implanted in the substrate, and the re-oxide layer will subsequently be removed (after the set of doping implants have been implanted). A set of spacers will then be formed along a set of side walls of the dummy gate and an epitaxial layer will be formed around the set of side walls. Thereafter, the dummy gate will be replaced with a metal gate (e.g., an aluminum or tungsten body having a high-k metal liner there-around).

Abstract translation: 提供了一种用于控制半导体器件的RMG的临界尺寸（CD）的方法。 具体地，本发明的实施例允许伪门和随后的RMG之间的CD一致性。 在典型的实施例中，在衬底上形成具有盖层的虚拟栅极。 然后在衬底上并围绕虚拟栅极形成再氧化物层。 然后将一组掺杂植入物植入衬底中，并且随后将去除再氧化物层（在植入了该组掺杂植入物之后）。 然后将沿着伪栅极的一组侧壁形成一组间隔物，并且将在该组侧壁周围形成外延层。 此后，虚拟栅极将被金属栅极（例如，具有高k金属衬垫的铝或钨体）替代。

公开(公告)号：US20210050419A1

公开(公告)日：2021-02-18

申请号：US16541600

申请日：2019-08-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Baofu Zhu ,  Haiting Wang ,  Sipeng Gu

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.

公开(公告)号：US10002793B1

公开(公告)日：2018-06-19

申请号：US15464591

申请日：2017-03-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  David P. Brunco ,  Jinping Liu ,  Baofu Zhu ,  Shesh Mani Pandey

IPC: H01L21/76 ,  H01L21/8234 ,  H01L21/761 ,  H01L21/225

CPC classification number: H01L21/2254 ,  H01L21/823431 ,  H01L21/823493 ,  H01L21/823821 ,  H01L21/823892

Abstract: A gap fill method for sub-fin doping includes forming semiconductor fin arrays over a semiconductor substrate, forming a first dopant source layer over a first fin array and filling intra fin gaps within the first array, and forming a second dopant source layer over a second fin array and filling intra fin gaps within the second array. The first and second dopant source layers are recessed to expose a channel region of the fins. Thereafter, an annealing step is used to drive dopants from the dopant source layers locally into sub-fin regions of the fins below the channel regions.

公开(公告)号：US20170288041A1

公开(公告)日：2017-10-05

申请号：US15091256

申请日：2016-04-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani Pandey ,  Baofu Zhu ,  Francis Benistant

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L29/66795 ,  H01L21/0217 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method includes forming a fin in a semiconductor substrate. An isolation structure is formed adjacent the fin. A first portion of the fin extends above the isolation structure. A gate electrode is formed above the first portion of the fin. A fin spacer is formed on the first portion of the fin. The fin spacer covers less than 50% of a height of the first portion of the fin. An implantation process is performed in the presence of the fin spacer to form a doped region in the first portion of the fin.

公开(公告)号：US20210043766A1

公开(公告)日：2021-02-11

申请号：US16533835

申请日：2019-08-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Baofu Zhu ,  Shesh Mani Pandey ,  Jiehui Shu ,  Sipeng Gu ,  Haiting Wang

IPC: H01L29/78 ,  H01L29/66

Abstract: A laterally diffused metal-oxide semiconductor (LDMOS) device is disclosed. The LDMOS FET includes a gate structure between a source region and a drain region over a p-type semiconductor substrate; and a trench isolation partially under the gate structure and between the gate structure and the drain region. A p-well is under and adjacent the source region; and an n-well is under and adjacent the drain region. A counter doping region abuts and is between the p-well and the n-well, and is directly underneath the gate structure. The counter doping region increases drain-source breakdown voltage compares to conventional approaches.

公开(公告)号：US20140273389A1

公开(公告)日：2014-09-18

申请号：US13799814

申请日：2013-03-13

Applicant: Globalfoundries Inc.

Inventor： Bingwu Liu ,  Baofu Zhu ,  Nam Sung Kim

IPC: H01L29/66

CPC classification number: H01L29/66545 ,  H01L21/28123 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78

Abstract: An approach for controlling a critical dimension (CD) of a RMG of a semiconductor device is provided. Specifically, embodiments of the present invention allow for CD consistency between a dummy gate and a subsequent RMG. In a typical embodiment, a dummy gate having a cap layer is formed over a substrate. A re-oxide layer is then formed over the substrate and around the dummy gate. A set of doping implants will then be implanted in the substrate, and the re-oxide layer will subsequently be removed (after the set of doping implants have been implanted). A set of spacers will then be formed along a set of side walls of the dummy gate and an epitaxial layer will be formed around the set of side walls. Thereafter, the dummy gate will be replaced with a metal gate (e.g., an aluminum or tungsten body having a high-k metal liner there-around).

Abstract translation: 提供了一种用于控制半导体器件的RMG的临界尺寸（CD）的方法。 具体地，本发明的实施例允许伪门和随后的RMG之间的CD一致性。 在典型的实施例中，在衬底上形成具有盖层的虚拟栅极。 然后在衬底上并围绕虚拟栅极形成再氧化物层。 然后将一组掺杂植入物植入衬底中，并且随后将去除再氧化物层（在植入了该组掺杂植入物之后）。 然后将沿着伪栅极的一组侧壁形成一组间隔物，并且将在该组侧壁周围形成外延层。 此后，虚拟栅极将被金属栅极（例如，具有高k金属衬垫的铝或钨体）替代。

公开(公告)号：US10910276B1

公开(公告)日：2021-02-02

申请号：US16589789

申请日：2019-10-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yongjun Shi ,  Xinyuan Dou ,  Chun Yu Wong ,  Hongliang Shen ,  Baofu Zhu

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/762 ,  H01L27/092 ,  H01L29/78

Abstract: A structure, an STI structure and a related method are disclosed. The structure may include an active region extending from a substrate; a gate extending over the active region; and a source/drain region in the active region, and an STI structure. The STI structure includes a liner and a fill layer on the liner along the opposed longitudinal sides of a lower portion of the active region, and the fill layer along the opposed ends of the active region. The liner may include a tensile stress-inducing liner that imparts a transverse-to-length tensile stress in at least a lower portion of the active region but not lengthwise. The liner can be applied in an n-FET region and/or a p-FET region to improve performance.

公开(公告)号：US20180108732A1

公开(公告)日：2018-04-19

申请号：US15292808

申请日：2016-10-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Baofu Zhu ,  Haifeng Sheng ,  Jinping Liu ,  Shesh Mani Pandey ,  Jagar Singh

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L29/0661 ,  H01L21/3083 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/7851

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to notched fin structures and methods of manufacture. The structure includes: a fin structure composed of a substrate material and a stack of multiple epitaxially grown materials on the substrate material; a notch formed in a first epitaxially grown material of the stack of multiple epitaxially grown materials of the fin structure; an insulator material within the notch of the fin structure; and an insulator layer surrounding the fin structure and above a surface of the notch.