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公开(公告)号:US20190131432A1
公开(公告)日:2019-05-02
申请号:US15795833
申请日:2017-10-27
申请人: GLOBALFOUNDRIES Inc.
发明人: Yi Qi , Sang Woo Lim , Kyung-Bum Koo , Alina Vinslava , Pei Zhao , Zhenyu Hu , Hsien-Ching Lo , Joseph F. Shepard, JR. , Shesh Mani Pandey
IPC分类号: H01L29/66 , H01L21/02 , H01L21/3065 , H01L29/08 , H01L29/161 , H01L29/16 , H01L29/165 , H01L29/78
CPC分类号: H01L29/66636 , H01L21/02529 , H01L21/02532 , H01L21/3065 , H01L21/845 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/66795 , H01L29/7848 , H01L29/7851
摘要: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.
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公开(公告)号:US10164099B2
公开(公告)日:2018-12-25
申请号:US15889367
申请日:2018-02-06
申请人: GLOBALFOUNDRIES Inc.
发明人: Shesh Mani Pandey , Pei Zhao , Baofu Zhu , Francis L. Benistant
IPC分类号: H01L29/78 , H01L29/08 , H01L29/16 , H01L29/165 , H01L29/66
摘要: One illustrative device disclosed herein includes, among other things, a fin defined on a substrate. A gate electrode structure is positioned above the fin in a channel region. A source/drain region is defined in the fin. The source/drain region includes a first epitaxial semiconductor material. The first epitaxial semiconductor material includes a dopant species having a first concentration. A diffusion blocking layer is positioned above the first epitaxial semiconductor material. A second epitaxial semiconductor material is positioned above the diffusion blocking layer. The second epitaxial semiconductor material includes the dopant species having a second concentration greater than the first concentration.
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公开(公告)号:US20180175198A1
公开(公告)日:2018-06-21
申请号:US15889367
申请日:2018-02-06
申请人: GLOBALFOUNDRIES Inc.
发明人: Shesh Mani Pandey , Pei Zhao , Baofu Zhu , Francis L. Benistant
IPC分类号: H01L29/78 , H01L29/66 , H01L29/08 , H01L29/165 , H01L29/16
CPC分类号: H01L29/7848 , H01L29/0847 , H01L29/1608 , H01L29/165 , H01L29/66636 , H01L29/66795 , H01L29/7851
摘要: One illustrative device disclosed herein includes, among other things, a fin defined on a substrate. A gate electrode structure is positioned above the fin in a channel region. A source/drain region is defined in the fin. The source/drain region includes a first epitaxial semiconductor material. The first epitaxial semiconductor material includes a dopant species having a first concentration. A diffusion blocking layer is positioned above the first epitaxial semiconductor material. A second epitaxial semiconductor material is positioned above the diffusion blocking layer. The second epitaxial semiconductor material includes the dopant species having a second concentration greater than the first concentration.
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公开(公告)号:US20170229578A1
公开(公告)日:2017-08-10
申请号:US15019273
申请日:2016-02-09
申请人: GLOBALFOUNDRIES Inc.
发明人: Shesh Mani Pandey , Pei Zhao , Baofu Zhu , Francis L. Benistant
IPC分类号: H01L29/78 , H01L29/66 , H01L29/165 , H01L29/08 , H01L29/16
CPC分类号: H01L29/7848 , H01L29/0847 , H01L29/1608 , H01L29/165 , H01L29/66636 , H01L29/66795 , H01L29/7851
摘要: A method includes forming a gate electrode structure above a channel region defined in a semiconductor material. The semiconductor material is recessed in a source/drain region. A first material is epitaxially grown in the source/drain region. The first material includes a dopant species having a first concentration. A diffusion blocking layer is formed in the source/drain region above the first material. A second material is epitaxially grown in the source/drain region above the diffusion blocking layer. The second material comprises the dopant species having a second concentration greater than the first concentration.
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公开(公告)号:US10056486B2
公开(公告)日:2018-08-21
申请号:US15079142
申请日:2016-03-24
申请人: GLOBALFOUNDRIES Inc.
发明人: Shesh Mani Pandey , Pei Zhao , Zhenyu Hu
IPC分类号: H01L29/78 , H01L29/66 , H01L29/08 , H01L29/161 , H01L29/16 , H01L29/165 , H01L29/24 , H01L29/267
CPC分类号: H01L29/7848 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/66545 , H01L29/66818 , H01L29/785 , H01L29/7851
摘要: Methods to reduce a width of a channel region of Si fins and the resulting devices are disclosed. Embodiments include forming a Si fin in a Si layer; forming a channel region over the Si fin including a dummy gate with a spacer on each side; forming S/D regions at opposite ends of the Si fin; removing the dummy gate, forming a cavity; thinning sidewalls of the Si fin; and forming a high-k/metal gate in the cavity.
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公开(公告)号:US09947788B2
公开(公告)日:2018-04-17
申请号:US15019273
申请日:2016-02-09
申请人: GLOBALFOUNDRIES Inc.
发明人: Shesh Mani Pandey , Pei Zhao , Baofu Zhu , Francis L. Benistant
IPC分类号: H01L29/78 , H01L29/08 , H01L29/16 , H01L29/165 , H01L29/66
CPC分类号: H01L29/7848 , H01L29/0847 , H01L29/1608 , H01L29/165 , H01L29/66636 , H01L29/66795 , H01L29/7851
摘要: A method includes forming a gate electrode structure above a channel region defined in a semiconductor material. The semiconductor material is recessed in a source/drain region. A first material is epitaxially grown in the source/drain region. The first material includes a dopant species having a first concentration. A diffusion blocking layer is formed in the source/drain region above the first material. A second material is epitaxially grown in the source/drain region above the diffusion blocking layer. The second material comprises the dopant species having a second concentration greater than the first concentration.
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公开(公告)号:US10355104B2
公开(公告)日:2019-07-16
申请号:US15795833
申请日:2017-10-27
申请人: GLOBALFOUNDRIES Inc.
发明人: Yi Qi , Sang Woo Lim , Kyung-Bum Koo , Alina Vinslava , Pei Zhao , Zhenyu Hu , Hsien-Ching Lo , Joseph F. Shepard, Jr. , Shesh Mani Pandey
IPC分类号: H01L21/02 , H01L21/84 , H01L29/66 , H01L21/3065 , H01L29/78 , H01L29/161 , H01L29/16 , H01L29/165 , H01L29/08
摘要: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.
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