公开(公告)号：US20160268204A1

公开(公告)日：2016-09-15

申请号：US15164114

申请日：2016-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L23/535 ,  H01L29/08 ,  H01L27/092 ,  H01L23/532 ,  H01L21/8238 ,  H01L21/285

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0847 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.

公开(公告)号：US09177963B2

公开(公告)日：2015-11-03

申请号：US14082263

申请日：2013-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anurag Mittal ,  Marc Tarabbia

IPC: H01L27/112 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/11206 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods for a low voltage antifuse device and the resulting devices are disclosed. Embodiments may include forming a plurality of fins above a substrate, removing a portion of a fin, forming a fin tip, forming a first area of a gate oxide layer above at least the fin tip, forming a second area of the gate oxide layer above a remaining portion of the plurality of fins, wherein the first area is thinner than the second area, and forming a gate over at least the fin tip to form an antifuse one-time programmable device.

Abstract translation: 公开了低压反熔丝装置的方法和所得装置。 实施例可以包括在基板上形成多个翅片，去除鳍片的一部分，形成翅片尖端，在至少鳍片尖端上形成栅极氧化物层的第一区域，形成上面的栅极氧化物层的第二区域 所述多个翅片的剩余部分，其中所述第一区域比所述第二区域薄，并且在至少所述翅片末端上形成栅极以形成反熔丝一次性可编程装置。

公开(公告)号：US09059093B2

公开(公告)日：2015-06-16

申请号：US14081736

申请日：2013-11-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Marc Tarabbia ,  Anurag Mittal ,  Nader Hindawy

IPC: H01L21/30 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/28158 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/823431 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/7856

Abstract: Methods for forming a variable fin FinFET cell wherein a plurality of fins is formed above a substrate, a portion of a fin is removed, forming a fin tip, a first area of a gate oxide layer is formed above the fin tip, and a second area of the gate oxide layer is formed above at least a remaining portion of the plurality of fins, wherein the first area is thicker than the second area.

Abstract translation: 用于形成可变翅片FinFET单元的方法，其中在基板上形成多个翅片，去除鳍片的一部分，形成翅片尖端，在翅片尖端上形成栅极氧化物层的第一区域，并且第二 栅极氧化物层的面积形成在多个翅片的至少剩余部分的上方，其中第一区域比第二区域厚。

公开(公告)号：US08975130B2

公开(公告)日：2015-03-10

申请号：US13930611

申请日：2013-06-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Roderick Miller ,  Marc Tarabbia

IPC: H01L21/8238 ,  H01L27/06 ,  H01L21/8249

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L29/0804 ,  H01L29/735 ,  H01L29/7851

Abstract: One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.

Abstract translation: 本文公开的一种方法包括执行至少一个公共处理操作，以形成用于多个场效应晶体管中的每一个的多个第一栅极结构和在将形成双极晶体管的区域上方的多个第二栅极结构，并且执行离子 注入工艺和加热工艺以形成在所有第二栅极结构下延伸的连续掺杂发射极区域。 本文公开的器件包括具有第一栅极结构的第一多个场效应晶体管，具有位于发射极区域上方的发射极区域和多个第二栅极结构的双极晶体管，其中所述双极晶体管包括延伸的连续掺杂发射极区域 在所有多个第二栅极结构的全部下方。