公开(公告)号：US09716487B1

公开(公告)日：2017-07-25

申请号：US15175578

申请日：2016-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sukeshwar Kannan ,  Luke G. England ,  Mehdi Z. Sadi

IPC: H03K3/011 ,  H03K5/131 ,  H03L7/197 ,  H03L7/00 ,  H03K5/14 ,  H03K3/037

CPC classification number: H03K3/011 ,  H03K3/037 ,  H03K5/131 ,  H03K5/14

Abstract: A latency compensation circuit and method. A three dimensional (3D) package is disclosed having a latency compensation circuit to address timing delays introduced by a through silicon via (TSV), including: an input for receiving a reference data signal from a redundant TSV and for receiving a local clock signal; a timing slack sensor that outputs a digital value reflecting a delay between a clock pulse of the local clock signal and the reference data signal; a look-up table that converts the digital value into a set of control bits; and an adjustable delay line that adjusts the local clock signal based on the set of control bits.