公开(公告)号：US20190304954A1

公开(公告)日：2019-10-03

申请号：US16447335

申请日：2019-06-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Luke G. England

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L25/00 ,  H01L21/3105 ,  H01L21/3213

Abstract: A 3D IC package includes a bottom die having a back interconnect side opposing a front device side, the back interconnect side having a plurality of bottom die interconnects extending thereto. A top die has a front device side opposing a back side, the front device side having a plurality of top die interconnects. An interposer includes a redistribution layer (RDL) between the bottom die and the top die, the RDL including a plurality of wiring layers extending from back side RDL interconnects thereof to front side RDL interconnects thereof. An under bump metallization (UBM) couples the back side RDL interconnects to the plurality of top die interconnects at a first location, and the front side RDL interconnects are coupled to the plurality of bottom die interconnects at a second location. The first location and second location may not overlap.

公开(公告)号：US10224286B1

公开(公告)日：2019-03-05

申请号：US15883693

申请日：2018-01-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Luke G. England ,  Kenneth J. Giewont

IPC: H01L23/538 ,  H01L23/49 ,  H01L21/768 ,  H01L21/48 ,  H01L25/16

Abstract: Embodiments of the disclosure provide an interconnect structure including: a first die having a first surface and an opposing second surface, and a groove within first surface of the first die; an adhesive dielectric layer mounted to the opposing second surface of the first die; a second die having a first surface mounted to the adhesive dielectric layer, and an opposing second surface, wherein the adhesive dielectric layer is positioned directly between the first and second dies; and a through-semiconductor via (TSV) including a first TSV metal extending from the first surface of the first die to the adhesive dielectric layer, and a second TSV metal substantially aligned with the first TSV metal and extending from the adhesive dielectric layer to the opposing second surface of the second die, wherein the TSV includes a metal-to-metal bonding interface between the first and second TSV metals within the adhesive dielectric layer.

公开(公告)号：US09865570B1

公开(公告)日：2018-01-09

申请号：US15431915

申请日：2017-02-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Luke G. England ,  Kathryn C. Rivera

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/367 ,  H01L23/373 ,  H01L23/29 ,  H01L23/522 ,  H01L21/56 ,  H01L21/48 ,  H01L21/683 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/78 ,  H01L23/00 ,  H01L23/04 ,  H01L23/10

CPC classification number: H01L25/0657 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/31053 ,  H01L21/4871 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/04 ,  H01L23/10 ,  H01L23/291 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/3736 ,  H01L23/5226 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/73204 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181

Abstract: Embodiments of the present disclosure relate to an integrated circuit (IC) package, including a molding compound positioned on a first die and laterally adjacent to a stack of dies positioned on the first die. The stack of dies electrically couples the first die to an uppermost die, and a thermally conductive pillar extends through the molding compound from the first die to an upper surface of the molding compound. The thermally conductive pillar is electrically isolated from the stack of dies and the uppermost die. The thermally conductive pillar laterally abuts and contacts the molding compound.

公开(公告)号：US09716487B1

公开(公告)日：2017-07-25

申请号：US15175578

申请日：2016-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sukeshwar Kannan ,  Luke G. England ,  Mehdi Z. Sadi

IPC: H03K3/011 ,  H03K5/131 ,  H03L7/197 ,  H03L7/00 ,  H03K5/14 ,  H03K3/037

CPC classification number: H03K3/011 ,  H03K3/037 ,  H03K5/131 ,  H03K5/14

Abstract: A latency compensation circuit and method. A three dimensional (3D) package is disclosed having a latency compensation circuit to address timing delays introduced by a through silicon via (TSV), including: an input for receiving a reference data signal from a redundant TSV and for receiving a local clock signal; a timing slack sensor that outputs a digital value reflecting a delay between a clock pulse of the local clock signal and the reference data signal; a look-up table that converts the digital value into a set of control bits; and an adjustable delay line that adjusts the local clock signal based on the set of control bits.

公开(公告)号：US20190237430A1

公开(公告)日：2019-08-01

申请号：US15882036

申请日：2018-01-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Luke G. England

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L21/683 ,  H01L25/00 ,  H01L21/3213 ,  H01L21/3105

CPC classification number: H01L25/0657 ,  H01L21/31053 ,  H01L21/32133 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/03 ,  H01L24/16 ,  H01L24/81 ,  H01L24/89 ,  H01L24/97 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/05025 ,  H01L2224/16227 ,  H01L2224/80006 ,  H01L2224/80009 ,  H01L2224/802 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81191 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/14

Abstract: A 3D IC package includes a bottom die having a back interconnect side opposing a front device side, the back interconnect side having a plurality of bottom die interconnects extending thereto. A top die has a front device side opposing a back side, the front device side having a plurality of top die interconnects. An interposer includes a redistribution layer (RDL) between the bottom die and the top die, the RDL including a plurality of wiring layers extending from back side RDL interconnects thereof to front side RDL interconnects thereof. An under bump metallization (UBM) couples the back side RDL interconnects to the plurality of top die interconnects at a first location, and the front side RDL interconnects are coupled to the plurality of bottom die interconnects at a second location. The first location and second location may not overlap.

公开(公告)号：US10283487B2

公开(公告)日：2019-05-07

申请号：US15826799

申请日：2017-11-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Luke G. England ,  Kathryn C. Rivera

IPC: H01L21/02 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/04 ,  H01L23/10 ,  H01L23/29 ,  H01L23/31 ,  H01L25/00 ,  H01L21/683 ,  H01L23/367 ,  H01L23/373 ,  H01L23/522 ,  H01L25/065 ,  H01L21/3105

Abstract: Embodiments of the present disclosure relate to an integrated circuit (IC) package, including a molding compound positioned on a first die and laterally adjacent to a stack of dies positioned on the first die. The stack of dies electrically couples the first die to an uppermost die, and a thermally conductive pillar extends through the molding compound from the first die to an upper surface of the molding compound. The thermally conductive pillar is electrically isolated from the stack of dies and the uppermost die. The thermally conductive pillar laterally abuts and contacts the molding compound.

公开(公告)号：US10163864B1

公开(公告)日：2018-12-25

申请号：US15678642

申请日：2017-08-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Luke G. England

IPC: H01L23/02 ,  H01L25/065 ,  H01L23/528 ,  H01L23/00 ,  H01L21/306 ,  H01L21/3105 ,  H01L25/00 ,  H01L21/768 ,  H01L21/683 ,  H01L23/522

Abstract: The disclosure is directed to an integrated circuit stack and method of forming the same. In one embodiment, the integrated circuit stack may include: a plurality of vertically stacked wafers, each wafer including a back side and a front side, the back side of each wafer including a through-semiconductor-via (TSV) within a substrate, and the front side of each wafer including a metal line within a first dielectric, wherein the metal line is connected with the TSV within each wafer; and an inorganic dielectric interposed between adjacent wafers within the plurality of vertically stacked wafer; wherein the plurality of vertically stacked wafers are stacked in a front-to-back orientation such that the TSV on the back side of one wafer is electrically connected to the metal line on the front side of an adjacent wafer by extending through the inorganic dielectric interposed therebetween.

公开(公告)号：US10388631B1

公开(公告)日：2019-08-20

申请号：US15882036

申请日：2018-01-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Luke G. England

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498 ,  H01L21/683 ,  H01L21/48 ,  H01L25/00 ,  H01L21/3213 ,  H01L21/3105

Abstract: A 3D IC package includes a bottom die having a back interconnect side opposing a front device side, the back interconnect side having a plurality of bottom die interconnects extending thereto. A top die has a front device side opposing a back side, the front device side having a plurality of top die interconnects. An interposer includes a redistribution layer (RDL) between the bottom die and the top die, the RDL including a plurality of wiring layers extending from back side RDL interconnects thereof to front side RDL interconnects thereof. An under bump metallization (UBM) couples the back side RDL interconnects to the plurality of top die interconnects at a first location, and the front side RDL interconnects are coupled to the plurality of bottom die interconnects at a second location. The first location and second location may not overlap.

公开(公告)号：US20180233488A1

公开(公告)日：2018-08-16

申请号：US15826799

申请日：2017-11-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Luke G. England ,  Kathryn C. Rivera

IPC: H01L25/065 ,  H01L21/02 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/04 ,  H01L23/10 ,  H01L23/29 ,  H01L23/31 ,  H01L23/367 ,  H01L23/373 ,  H01L23/522 ,  H01L23/00 ,  H01L25/00 ,  H01L21/3105

CPC classification number: H01L25/0657 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/31053 ,  H01L21/4871 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/04 ,  H01L23/10 ,  H01L23/291 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/3736 ,  H01L23/5226 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161

Abstract: Embodiments of the present disclosure relate to an integrated circuit (IC) package, including a molding compound positioned on a first die and laterally adjacent to a stack of dies positioned on the first die. The stack of dies electrically couples the first die to an uppermost die, and a thermally conductive pillar extends through the molding compound from the first die to an upper surface of the molding compound. The thermally conductive pillar is electrically isolated from the stack of dies and the uppermost die. The thermally conductive pillar laterally abuts and contacts the molding compound.