公开(公告)号：US10340180B1

公开(公告)日：2019-07-02

申请号：US15872314

申请日：2018-01-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hsueh-Chung Chen ,  Martin J. O'Toole ,  Terry A. Spooner ,  Jason E. Stephens

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/033 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/53271

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to merged mandrel lines and methods of manufacture. The structure includes: at least one metal line having a first dimension in a self-aligned double patterning (SADP) line array; and at least one metal line having a second dimension inserted into the SADP line array, the second dimension being different than the first dimension.

公开(公告)号：US10192780B1

公开(公告)日：2019-01-29

申请号：US15991529

申请日：2018-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiaohan Wang ,  Jiehui Shu ,  Brendan O'Brien ,  Terry A. Spooner ,  Jinping Liu ,  Ravi Prakash Srivastava

IPC: H01L29/40 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: Methods of self-aligned double patterning and improved interconnect structures formed by self-aligned double patterning. A mandrel line including an upper layer and a lower layer is formed over a hardmask. A non-mandrel cut block is formed over a portion of a non-mandrel line, after which the upper layer of the mandrel line is removed. An etch mask is formed over a first section of the lower layer of the mandrel line defining a mandrel cut block over a first portion of the hardmask. The first section of the lower layer is arranged between adjacent second sections of the lower layer. The second sections of the lower layer of the mandrel line are removed to expose respective second portions of the hardmask, and the second portions of the hardmask are removed to form a trench. The mandrel cut block masks the first portion of the hardmask during the etching process.

公开(公告)号：US09490168B1

公开(公告)日：2016-11-08

申请号：US14710894

申请日：2015-05-13

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Shyng-Tsong Chen ,  Cheng Chi ,  Chi-Chun Liu ,  Sylvie M. Mignot ,  Yann A. Mignot ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wenhui Wang ,  Yongan Xu

IPC: H01L21/28 ,  H01L21/768 ,  H01L23/535 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

Abstract translation: 提供了形成通孔到半导体器件的下层的方法。 该方法可以包括使用侧壁图像转移过程在下层上形成柱。 介电层形成在柱和下层之上; 以及图案化在所述电介质层上的通孔掩模，所述通孔掩模具有至少部分地与所述支柱重叠的掩模开口。 使用通孔掩模在电介质层中蚀刻通孔开口，掩模开口在第一方向上限定通孔开口的第一横向尺寸，并且柱沿不同于第一方向的第二方向限定通孔开口的第二横向尺寸 方向。 通孔开口填充有导体以形成通孔。 还提供了半导体器件和通孔结构。