公开(公告)号：US10121846B1

公开(公告)日：2018-11-06

申请号：US15620923

申请日：2017-06-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alban Zaka ,  Ignasi Cortes Mayol ,  Tom Herrmann ,  El Mehdi Bazizi ,  John Morgan

IPC: H01L49/02 ,  H01L27/06

Abstract: The present disclosure provides resistor structures in sophisticated integrated circuits on the basis of an SOI architecture, wherein a very thin semiconductor layer, typically used for forming fully depleted SOI transistors, may be used as a resistor body. In this manner, significantly higher sheet resistance values may be achieved, thereby providing the potential for implementing high ohmic resistors into sophisticated integrated circuits.

公开(公告)号：US10580863B2

公开(公告)日：2020-03-03

申请号：US15728679

申请日：2017-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Damien Angot ,  Alban Zaka ,  Tom Herrmann ,  Venkata Naga Ranjith Kuma Nelluri ,  Jan Hoentschel ,  Lars Mueller-Meskamp ,  Martin Gerhardt

IPC: H01L27/088 ,  H01L21/336 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/10 ,  H01L21/84 ,  H01L29/66 ,  H01L21/225 ,  H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: In sophisticated semiconductor devices, the lateral electric field in fully depleted transistor elements operated at elevated supply voltages may be significantly reduced by establishing a laterally graded dopant profile at edge regions of the respective channel regions. In some illustrative embodiments to this end, one or more dopant species may be incorporated prior to completing the gate electrode structure.

公开(公告)号：US20190157451A1

公开(公告)日：2019-05-23

申请号：US15819825

申请日：2017-11-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ignasi Cortes Mayol ,  Alban Zaka ,  Tom Herrmann ,  El Mehdi Bazizi

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an LDMOS device on FDSOI structures and methods of manufacture. The laterally double diffused semiconductor device includes a gate dielectric composed of a buried insulator material of a semiconductor on insulator (SOI) technology, a channel region composed of semiconductor material of the SOI technology and source/drain regions on a front side of the buried insulator material such that a gate is formed on a back side of the buried insulator material. The gate terminal can also be placed at a hybrid section used as a back-gate voltage to control the channel and the drift region of the device.

公开(公告)号：US20180090558A1

公开(公告)日：2018-03-29

申请号：US15277583

申请日：2016-09-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alban Zaka ,  Ignasi Cortes Mayol ,  Tom Herrmann ,  Andrei Sidelnicov ,  El Mehdi Bazizi

IPC: H01L49/02 ,  H01L23/535 ,  H01L29/36

CPC classification number: H01L28/60 ,  H01L23/535 ,  H01L29/94

Abstract: A capacitor, such as an N-well capacitor, in a semiconductor device includes a floating semiconductor region, which allows a negative biasing of the channel region of the capacitor while suppressing leakage into the depth of the substrate. In this manner, N-well-based capacitors may be provided in the device level and may have a substantially flat capacitance/voltage characteristic over a moderately wide range of voltages. Consequently, alternating polarity capacitors formed in the metallization system may be replaced by semiconductor-based N-well capacitors.