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    ASYMMETRIC LATERAL BIPOLAR TRANSISTOR AND METHOD
    11.
    发明申请
    ASYMMETRIC LATERAL BIPOLAR TRANSISTOR AND METHOD 有权

    公开(公告)号：US20230032080A1

    公开(公告)日：2023-02-02

    申请号：US17388284

    申请日：2021-07-29

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Alexander M. Derrickson ,  Mankyu Yang ,  Judson R. Holt ,  Jagar Singh ,  Alexander L. Martin ,  Richard F. Taylor, III

    IPC: H01L29/735 ,  H01L29/417 ,  H01L29/08 ,  H01L29/66

    Abstract: Disclosed is a semiconductor structure that includes an asymmetric lateral bipolar junction transistor (BJT). The BJT includes an emitter, a base, a collector extension and a collector arranged side-by-side (i.e., laterally) across a semiconductor layer. The emitter, collector and collector extension have a first type conductivity with the collector extension having a lower conductivity level than either the emitter or the collector. The base has a second type conductivity that is different from the first type conductivity. With such a lateral configuration, the BJT can be easily integrated with CMOS devices on advanced SOI technology platforms. With such an asymmetric configuration and, particularly, given the inclusion of the collector extension but not an emitter extension, the BJT can achieve a relatively high collector-emitter breakdown voltage (Vbr-CEO) without a significant risk of leakage currents at high voltages. Also disclosed are method embodiments for forming such a semiconductor structure.

    Silicon-on-insulator chip structure with substrate-embedded optical waveguide and method
    12.
    发明授权
    Silicon-on-insulator chip structure with substrate-embedded optical waveguide and method 有权

    公开(公告)号：US11448822B2

    公开(公告)日：2022-09-20

    申请号：US17131997

    申请日：2020-12-23

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Judson R. Holt ,  Yusheng Bian ,  Dali Shao

    IPC: G02B6/12 ,  G02B6/122 ,  H01L29/06 ,  G02B6/30

    Abstract: Disclosed is a silicon-on-insulator (SOI) chip structure with a substrate-embedded optical waveguide. Also disclosed is a method for forming the SOI chip structure. In the method, an optical waveguide is formed within a trench in a bulk substrate prior to a wafer bonding process that results in the SOI structure. Subsequently, front-end-of-the-line (FEOL) processing can be performed to form additional optical devices and/or electronic devices in and/or above the silicon layer. By embedding an optical waveguide within the substrate prior to wafer bonding as opposed to forming it during FEOL processing, strict limitations on the dimensions of the core layer of the optical waveguide are avoided. The core layer of the substrate-embedded optical waveguide can be relatively large such that the cut-off wavelength can be relatively long. Thus, such a substrate-embedded optical waveguide brings different functionality to the SOI chip structure as compared to FEOL optical waveguides.

    BIPOLAR JUNCTION TRANSISTORS WITH A WRAPAROUND BASE LAYER
    14.
    发明申请
    BIPOLAR JUNCTION TRANSISTORS WITH A WRAPAROUND BASE LAYER 有权

    公开(公告)号：US20220262930A1

    公开(公告)日：2022-08-18

    申请号：US17176251

    申请日：2021-02-16

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Vibhor Jain ,  Judson R. Holt ,  Tayel Nesheiwat ,  John J. Pekarik ,  Christopher Durcan

    IPC: H01L29/732 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

    Abstract: Device structures and fabrication methods for a bipolar junction transistor. The device structure includes a substrate and a trench isolation region in the substrate. The trench isolation region surrounds an active region of the substrate. The device structure further includes a collector in the active region of the substrate, a base layer having a first section positioned on the active region and a second section oriented at an angle relative to the first section, an emitter positioned on the first section of the base layer, and an extrinsic base layer positioned over the trench isolation region and adjacent to the emitter. The second section of the base layer is laterally positioned between the extrinsic base layer and the emitter.

    Limiting lateral epitaxy growth at N-P boundary using inner spacer, and related structure
    15.
    发明授权
    Limiting lateral epitaxy growth at N-P boundary using inner spacer, and related structure 有权

    公开(公告)号：US11217584B2

    公开(公告)日：2022-01-04

    申请号：US16660868

    申请日：2019-10-23

    Applicant: GLOBALFOUNDRIES U.S. INC.

    Inventor： Judson R. Holt ,  Jiehui Shu

    IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L21/82 ,  H01L29/66

    Abstract: A method limits lateral epitaxy growth at an N-P boundary area using an inner spacer. The method may include forming inner spacers on inner sidewalls of the inner active regions of a first polarity region (e.g., n-type) and an adjacent second polarity region (e.g., p-type) that are taller than any outer spacers on an outer sidewall of the inner active regions. During forming of semiconductor layers over the active regions (e.g., via epitaxy), the inner spacers abut and limit lateral forming of the semiconductor layers. The method generates larger semiconductor layers than possible with conventional approaches, and prevents electrical shorts between the semiconductor layers in an N-P boundary area. A structure includes the semiconductor epitaxy layers separated from one another, and abutting respective inner spacers. Any outer spacer on the inner active region is shorter than a respective inner spacer.

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