公开(公告)号：US20240363777A1

公开(公告)日：2024-10-31

申请号：US18764436

申请日：2024-07-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Ming Chen ,  Lee-Chuan Tseng ,  Ming Chyi Liu ,  Po-Chun Liu

IPC: H01L31/0352 ,  H01L31/02 ,  H01L31/0216 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/103 ,  H01L31/105 ,  H01L31/18

CPC classification number: H01L31/035281 ,  H01L31/02005 ,  H01L31/02019 ,  H01L31/02161 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/103 ,  H01L31/1037 ,  H01L31/105 ,  H01L31/1808 ,  H01L31/1812 ,  Y02E10/547

Abstract: Some embodiments relate to an integrated circuit (IC) disposed on a silicon substrate, which includes a well region having a first conductivity type. An epitaxial pillar of SiGe or Ge extends upward from the well region. The epitaxial pillar includes a lower epitaxial region having the first conductivity type and an upper epitaxial region having a second conductivity type, which is opposite the first conductivity type. A dielectric layer is arranged over an upper surface of the substrate and is disposed around the lower epitaxial region to extend over outer edges of the well region. The dielectric layer has inner sidewalls that contact outer sidewalls of the epitaxial pillar. A dielectric sidewall structure has a bottom surface that rests on an upper surface of the dielectric layer and has inner sidewalls that extend continuously from the upper surface of the dielectric layer to a top surface of the epitaxial pillar.

公开(公告)号：US20240243216A1

公开(公告)日：2024-07-18

申请号：US18413897

申请日：2024-01-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungsang CHO ,  Chanwook BAIK ,  Yooseong YANG

IPC: H01L31/113 ,  H01L31/028 ,  H01L31/18

CPC classification number: H01L31/1136 ,  H01L31/028 ,  H01L31/1808

Abstract: A light sensing device includes a channel layer, a first electrode provided on a first surface of the channel layer, a second electrode provided on the first surface of the channel layer and spaced apart from the first electrode, and a light absorption layer provided on the channel layer between the first electrode and the second electrode and configured to absorb infrared rays, where the light absorption layer includes a doped semiconductor layer.

公开(公告)号：US20240079515A1

公开(公告)日：2024-03-07

申请号：US18388286

申请日：2023-11-09

Applicant: AZUR SPACE Solar Power GmbH

Inventor： Alexander FREY ,  Benjamin HAGEDORN

IPC: H01L31/18 ,  H01L31/0216 ,  H01L31/0224 ,  H01L31/0384

CPC classification number: H01L31/1808 ,  H01L31/02167 ,  H01L31/02245 ,  H01L31/0384 ,  H01L31/1852 ,  H01L31/1868 ,  Y02E10/544

Abstract: A method for structuring an insulating layer on a semiconductor wafer includes providing a semiconductor wafer with a top, a bottom and includes multiple solar cell stacks, wherein each solar cell stack is a Ge substrate, which forms the bottom of the semiconductor wafer, a Ge subcell and at least two III-V subcells, in the above order, and at least one passage opening, which extends from the top to the bottom of the semiconductor wafer and has a connected side wall, an insulating layer two-dimensionally deposited on the top of the semiconductor wafer, on the side wall of the passage opening and/or on the bottom of the semiconductor wafer, and the deposition of an etch-resistant filling material by means of a printing process on an area of the top which include the passage opening, and into the passage opening.

公开(公告)号：US20230369521A1

公开(公告)日：2023-11-16

申请号：US18350813

申请日：2023-07-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Ming Chen ,  Lee-Chuan Tseng ,  Ming Chyi Liu ,  Po-Chun Liu

IPC: H01L31/0352 ,  H01L31/02 ,  H01L31/0216 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/103 ,  H01L31/105 ,  H01L31/18

CPC classification number: H01L31/035281 ,  H01L31/02005 ,  H01L31/02019 ,  H01L31/02161 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/103 ,  H01L31/1037 ,  H01L31/105 ,  H01L31/1808 ,  H01L31/1812 ,  Y02E10/547

Abstract: Some embodiments relate to an integrated circuit (IC) disposed on a silicon substrate, which includes a well region having a first conductivity type. An epitaxial pillar of SiGe or Ge extends upward from the well region. The epitaxial pillar includes a lower epitaxial region having the first conductivity type and an upper epitaxial region having a second conductivity type, which is opposite the first conductivity type. A dielectric layer is arranged over an upper surface of the substrate and is disposed around the lower epitaxial region to extend over outer edges of the well region. The dielectric layer has inner sidewalls that contact outer sidewalls of the epitaxial pillar. A dielectric sidewall structure has a bottom surface that rests on an upper surface of the dielectric layer and has inner sidewalls that extend continuously from the upper surface of the dielectric layer to a top surface of the epitaxial pillar.

公开(公告)号：US11791432B2

公开(公告)日：2023-10-17

申请号：US17182954

申请日：2021-02-23

Applicant: W&WSens Devices, Inc.

Inventor： Shih-Yuan Wang ,  Shih-Ping Wang

IPC: H01L27/146 ,  H01L31/0236 ,  H01L31/0352 ,  H01L31/18 ,  H01L27/144 ,  H04B10/69 ,  H01L31/02 ,  H01L31/0232 ,  H01L31/09 ,  H01L31/103 ,  H01L31/028 ,  H01L31/107 ,  H04B10/25 ,  H04B10/40 ,  H04B10/80 ,  G02B1/00 ,  G02B6/42 ,  H01L31/077 ,  H01L31/036 ,  H01L31/075 ,  H01L31/105

CPC classification number: H01L27/14607 ,  G02B1/002 ,  G02B6/4204 ,  G02B6/428 ,  H01L27/1443 ,  H01L27/1446 ,  H01L27/14625 ,  H01L31/02 ,  H01L31/028 ,  H01L31/02016 ,  H01L31/0232 ,  H01L31/0236 ,  H01L31/02325 ,  H01L31/02327 ,  H01L31/02363 ,  H01L31/02366 ,  H01L31/036 ,  H01L31/0352 ,  H01L31/035218 ,  H01L31/035281 ,  H01L31/075 ,  H01L31/077 ,  H01L31/09 ,  H01L31/103 ,  H01L31/105 ,  H01L31/107 ,  H01L31/1075 ,  H01L31/1804 ,  H01L31/1808 ,  H04B10/25 ,  H04B10/40 ,  H04B10/691 ,  H04B10/6971 ,  H04B10/801 ,  G02B1/005 ,  Y02E10/547 ,  Y02P70/50

Abstract: Lateral and vertical microstructure enhanced photodetectors and avalanche photodetectors are monolithically integrated with CMOS/BiCMOS ASICs and can also be integrated with laser devices using fluidic assembly techniques. Photodetectors can be configured in a vertical PIN arrangement or lateral metal-semiconductor-metal arrangement where electrodes are in an inter-digitated pattern. Microstructures, such as holes and protrusions, can improve quantum efficiency in silicon, germanium and III-V materials and can also reduce avalanche voltages for avalanche photodiodes. Applications include optical communications within and between datacenters, telecommunications, LIDAR, and free space data communication.

公开(公告)号：US20230282476A1

公开(公告)日：2023-09-07

申请号：US17683567

申请日：2022-03-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Lung Yuan Pan ,  Chen-Hao Chiang ,  Chih-Ming Chen

IPC: H01L21/02 ,  H01L21/762 ,  H01L31/0352 ,  H01L31/105 ,  H01L31/18

CPC classification number: H01L21/02532 ,  H01L21/76251 ,  H01L21/0262 ,  H01L31/035281 ,  H01L31/105 ,  H01L31/1808

Abstract: In some embodiments, the present disclosure relates to a semiconductor device, including a substrate including a first semiconductor material and a semiconductor layer extending into an upper surface of the substrate and including a second semiconductor material with a different band gap than the first semiconductor material. The semiconductor device also includes a passive cap including a first dielectric material and disposed along the upper surface of the substrate and on opposite sides of the semiconductor layer, and a photodetector in the semiconductor layer. The first dielectric material includes silicon nitride.

公开(公告)号：US20180342634A1

公开(公告)日：2018-11-29

申请号：US16030134

申请日：2018-07-09

Applicant: Elenion Technologies, LLC

Inventor： Thomas Wetteland Baehr-Jones ,  Yi Zhang ,  Michael J. Hochberg ,  Ari Novack

IPC: H01L31/0352 ,  H01L31/105 ,  H01L27/146 ,  H01L31/0256 ,  H01L31/18 ,  H01L31/107 ,  H01L31/028

CPC classification number: H01L31/0352 ,  H01L27/14638 ,  H01L27/14649 ,  H01L27/14685 ,  H01L27/14698 ,  H01L31/0256 ,  H01L31/028 ,  H01L31/105 ,  H01L31/107 ,  H01L31/1808 ,  Y02E10/547

Abstract: A Ge-on-Si photodetector constructed without doping or contacting Germanium by metal is described. Despite the simplified fabrication process, the device has responsivity of 1.24 A/W, corresponding to 99.2% quantum efficiency. Dark current is 40 nA at −4 V reverse bias. 3-dB bandwidth is 30 GHz.

公开(公告)号：US10043938B2

公开(公告)日：2018-08-07

申请号：US15467669

申请日：2017-03-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Barry P. Linder ,  Jason S. Orcutt

IPC: H01L31/18 ,  H01L21/66 ,  H01L31/024 ,  H01L31/028 ,  G01R19/00 ,  H01L31/0203 ,  H01L31/105

CPC classification number: H01L31/1864 ,  G01R19/0092 ,  H01L22/20 ,  H01L22/26 ,  H01L31/0203 ,  H01L31/024 ,  H01L31/028 ,  H01L31/105 ,  H01L31/1808 ,  H01L31/186 ,  H05K999/00 ,  H05K999/99 ,  Y02E10/50

Abstract: Methods and systems for reducing dark current in a photodiode include heating a photodiode above room temperature. A reverse bias voltage is applied to the heated photodiode to reduce a dark current generated by the photodiode.

公开(公告)号：US09934967B2

公开(公告)日：2018-04-03

申请号：US13737731

申请日：2013-01-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jennifer M. Hydrick ,  Jizhong Li ,  Zhinyuan Cheng ,  James Fiorenza ,  Jie Bai ,  Ji-Soo Park ,  Anthony J. Lochtefeld

IPC: H01L31/18 ,  H01L31/0687 ,  H01L29/205 ,  H01L21/02

CPC classification number: H01L21/02538 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02647 ,  H01L29/205 ,  H01L31/0687 ,  H01L31/06875 ,  H01L31/1808 ,  H01L31/1852 ,  H01L31/1892 ,  Y02E10/544

Abstract: Methods and structures are provided for formation of devices, e.g., solar cells, on substrates including, e.g., lattice-mismatched materials, by the use of aspect ratio trapping and epitaxial layer overgrowth. A method includes forming an opening in a masking layer disposed over a substrate that includes a first semiconductor material. A first layer, which includes a second semiconductor material lattice-mismatched to the first semiconductor material, is formed within the opening. The first layer has a thickness sufficient to extend above a top surface of the masking layer. A second layer, which includes the second semiconductor material, is formed on the first layer and over at least a portion of the masking layer. A vertical growth rate of the first layer is greater than a lateral growth rate of the first layer and a lateral growth rate of the second layer is greater than a vertical growth rate of the second layer.

公开(公告)号：US20180090631A1

公开(公告)日：2018-03-29

申请号：US15273880

申请日：2016-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Lee-Chuan Tseng ,  Ming Chyi Liu ,  Po-Chun Liu

IPC: H01L31/0352 ,  H01L31/0216 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/02 ,  H01L31/103 ,  H01L31/105 ,  H01L31/18

CPC classification number: H01L31/035281 ,  H01L31/02005 ,  H01L31/02019 ,  H01L31/02161 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/103 ,  H01L31/1037 ,  H01L31/105 ,  H01L31/1808 ,  H01L31/1812

Abstract: Some embodiments relate to an integrated circuit (IC) disposed on a silicon substrate, which includes a well region having a first conductivity type. A dielectric layer is arranged over an upper surface of the silicon substrate, and extends over outer edges of the well region and includes an opening that leaves an inner portion of the well region exposed. An epitaxial pillar of SiGe or Ge extends upward from the inner portion of the well region. The epitaxial pillar includes a lower epitaxial region having the first conductivity type and an upper epitaxial region having a second conductivity type, which is opposite the first conductivity type. A dielectric sidewall structure surrounds the epitaxial pillar and has a bottom surface that rests on an upper surface of the dielectric layer.