公开(公告)号：US07724854B2

公开(公告)日：2010-05-25

申请号：US11138508

申请日：2005-05-26

申请人： George S. Moore

发明人： George S. Moore

IPC分类号： H04L7/00

CPC分类号： H04J3/0685 ,  H04L7/0041

摘要： In one embodiment, a system comprises a signal source for generating a digital signal in response to a data pull signal; a digital-to-analog converter (DAC); a first plurality of shift registers for registering digital words of the digital signal before receipt by the DAC; a synchronizing logic element for generating the data pull signal, wherein the synchronizing logic element initially generates the data pull signal to cause the signal source to generate a number of data words, ceases communication of the data pull signal upon receipt of a mark signal, and resumes communication of the data pull signal upon receipt of a trigger signal; and a second plurality of shift registers for registering the mark signal before communication to the synchronizing logic element, wherein the first and second plurality of shift registers are enabled by the data pull signal.

摘要翻译： 在一个实施例中，系统包括用于响应于数据拉动信号产生数字信号的信号源; 数模转换器（DAC）; 第一多个移位寄存器，用于在由DAC接收之前注册数字信号的数字字; 用于产生所述数据拉动信号的同步逻辑元件，其中所述同步逻辑元件最初产生所述数据拉动信号以使得所述信号源产生多个数据字，在接收到标记信号时停止所述数据拉动信号的通信，以及 在接收到触发信号时恢复数据拉出信号的通信; 以及第二多个移位寄存器，用于在通信之前将标记信号注册到同步逻辑元件，其中第一和第二多个移位寄存器由数据拉取信号使能。

公开(公告)号：US07136770B2

公开(公告)日：2006-11-14

申请号：US10700831

申请日：2003-11-03

申请人： Jochen Rivoir ,  John McLaughlin ,  Joseph M. Gorin ,  Moray Denham Rumney ,  Matthew Johnson ,  Robert Locascio ,  Peter J. Cain ,  David H. Molinari ,  George S. Moore

发明人： Jochen Rivoir ,  John McLaughlin ,  Joseph M. Gorin ,  Moray Denham Rumney ,  Matthew Johnson ,  Robert Locascio ,  Peter J. Cain ,  David H. Molinari ,  George S. Moore

IPC分类号： G01R31/00 ,  G01R31/14

CPC分类号： G06F11/3447

摘要： Using component-level test data to reduce system test. By modeling a system, sensitivity analysis reveals critical components and parameters of those components required to meet system performance parameters. Critical components are tested for these parameters, and these measurements associated with the components. Systems may be assembled which are modeled to meet the system performance parameters based on the model and the measured parameters. Systems may be assembled and calibration coefficients derived and applied from the model and the measured parameters.

摘要翻译： 使用组件级测试数据来减少系统测试。 通过对系统建模，灵敏度分析揭示了满足系统性能参数所需的关键组件和参数。 对这些参数测试关键部件，这些测量与组件相关。 可以组装系统，其被建模以基于模型和测量的参数来满足系统性能参数。 可以组装系统并从模型和测量参数导出和应用校准系数。

公开(公告)号：US5031168A

公开(公告)日：1991-07-09

申请号：US521187

申请日：1990-05-09

申请人： George S. Moore

发明人： George S. Moore

IPC分类号： G11B5/004 ,  G11B5/008 ,  G11B5/012 ,  G11B5/09 ,  G11B7/007 ,  G11B7/013 ,  G11B9/10 ,  G11B11/105 ,  G11B20/10

CPC分类号： G11B7/24085 ,  G11B11/10528 ,  G11B20/10 ,  G11B5/004 ,  G11B5/00804 ,  G11B5/012 ,  G11B5/09 ,  G11B7/24079 ,  G11B9/10

摘要： An improved method of configuring digital information in a recording storage media so as to significantly increase the information storage capacity of the media, and the media containing such configured digital information are disclosed. Information containing markers are arranged and configured along tracks in the media in a manner such that markers of adjacent tracks are offset relative to one another. Inter-track spacings of arcuately shaped tracks on a storage media are progressively reduced as a function of the radial spacing of the tracks from their center of curvature, further increasing the marker packing density. Return to zero pulsed modulation schemes are employed to maximize the amount of information recorded in a given number of marker locations. Drive means for reading digital information configured on storage media according to the principles of this invention are provided.

摘要翻译： 公开了一种在记录存储介质中配置数字信息以便显着增加媒体的信息存储能力以及包含这种配置的数字信息的介质的改进方法。 包含标记的信息沿着媒体中的轨道被布置和配置，使得相邻轨道的标记相对于彼此偏移。 存储介质上的弧形轨道的轨道间距随着轨道与其曲率中心的径向间距的函数而逐渐减小，进一步增加了标记填充密度。 使用零脉冲调制方案来最大化在给定数量的标记位置中记录的信息量。 提供了用于读取根据本发明的原理在存储介质上配置的数字信息的驱动装置。