公开(公告)号：US20170141109A1

公开(公告)日：2017-05-18

申请号：US15420967

申请日：2017-01-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navneet JAIN ,  Juhan KIM ,  Andy NGUYEN ,  Mahbub RASHED

IPC: H01L27/088 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/02 ,  H01L29/08 ,  H01L21/8234 ,  H01L23/528

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.

公开(公告)号：US20150187702A1

公开(公告)日：2015-07-02

申请号：US14645598

申请日：2015-03-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mahbub RASHED ,  Yuansheng MA ,  Irene LIN ,  Jason STEPHENS ,  Yunfei DENG ,  Lei YUAN ,  Jongwook KYE ,  Rod AUGUR ,  Shibly AHMED ,  Subramani KENGERI ,  Suresh VENKATESAN

IPC: H01L23/538 ,  H01L27/092 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L23/5386 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/5384 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.

Abstract translation: 公开了一种使用扩散接触结构提供MOL构造的方法。 实施例包括：在衬底中提供第一扩散区域; 经由第一光刻工艺提供第一扩散接触结构; 经由第二光刻工艺提供第二扩散接触结构; 以及将所述第一扩散接触结构耦合到所述第一扩散区和所述第二扩散接触结构。 实施例包括：在衬底中提供第二扩散区域; 在所述第一和第二扩散区之间提供扩散间隙区域; 在所述扩散间隙区域上提供所述扩散接触结构; 以及经由扩散接触结构耦合第一和第二扩散区域。

公开(公告)号：US20150311122A1

公开(公告)日：2015-10-29

申请号：US14263399

申请日：2014-04-28

Applicant: Globalfoundries Inc.

Inventor： Mahbub RASHED ,  Yunfei DENG ,  Juhan KIM ,  Jongwook KYE ,  Suresh VENKATESAN ,  Subramani KENGERI

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886

Abstract: Methods for forming abutting FinFET cells with a single dummy gate and continuous fins, and the resulting devices, are disclosed. Embodiments may include forming one or more continuous fins on a substrate, forming gates perpendicular to and over the one or more continuous fins to form a first FinFET cell and a second FinFET cell, and forming source and drain contact lines parallel to and between the gates, wherein a source contact line of the first FinFET cell is adjacent to a drain contact line of the second FinFET cell, and the source contact line and the drain contact line are on opposite sides of a gate.

Abstract translation: 公开了用于形成具有单个虚拟栅极和连续散热片的邻接FinFET单元的方法以及所得到的器件。 实施例可以包括在基板上形成一个或多个连续的翅片，形成垂直于一个或多个连续翅片上方和上方的栅极以形成第一FinFET单元和第二FinFET单元，以及形成平行于栅极和栅极之间的源极和漏极接触线 ，其中所述第一FinFET单元的源极接触线与所述第二FinFET单元的漏极接触线相邻，并且所述源极接触线和所述漏极接触线位于栅极的相对侧上。