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公开(公告)号：US20240203630A1
公开(公告)日：2024-06-20
申请号：US18590577
申请日：2024-02-28
Applicant: Google LLC
Inventor： Houle Gan , Shuai Jiang , Gregory Sizikov , Xin Li , Chee Yee Chung
CPC classification number: H01F17/0006 , H05K5/0069
Abstract: The disclosure relates to power modules that include elevated inductors with capacitors disposed under the inductors. In one aspect, a power module includes a first circuit board having a first surface and a second surface opposite the first surface. One or more inductors are mounted on the first surface. Each of the one or more inductors includes a top surface and a bottom surface opposite the top surface and that faces the first surface of the first circuit board. Each inductor is elevated above the first surface of the first circuit board such that at least a portion of the bottom surface of the inductor does not contact the first surface of the first circuit board. The first circuit board includes capacitors arranged in an area below the portion of the bottom surface of the inductor that does not contact the first surface of the first circuit board.
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公开(公告)号：US20240120847A1
公开(公告)日：2024-04-11
申请号：US17961264
申请日：2022-10-06
Applicant: Google LLC
Inventor： Shuai Jiang , Xin Li , Woon-Seong Kwon , Cheng Chung Yang , Qiong Wang , Nam Hoon Kim , Mikhail Popovich , Houle Gan , Chenhao Nan
CPC classification number: H02M3/33576 , H02M1/0067 , H02M3/33571
Abstract: A voltage regulator having a multiple of main stages and at least one accelerated voltage regulator (AVR) bridge is provided. The main stages may respond to low frequency current transients and provide DC output voltage regulation. The AVR bridges are switched much faster than the main stages and respond to high frequency current transients without regulating the DC output voltage. The AVR bridge frequency response range can overlap with the main stage frequency response range, and the lowest frequency to which the AVR bridges respond may be set lower than the highest frequency to which the main stages respond.
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公开(公告)号：US11948716B1
公开(公告)日：2024-04-02
申请号：US16800776
申请日：2020-02-25
Applicant: Google LLC
Inventor： Houle Gan , Shuai Jiang , Gregory Sizikov , Xin Li , Chee Yee Chung
CPC classification number: H01F17/0006 , H05K5/0069
Abstract: The disclosure relates to power modules that include elevated inductors with capacitors disposed under the inductors. In one aspect, a power module includes a first circuit board having a first surface and a second surface opposite the first surface. One or more inductors are mounted on the first surface. Each of the one or more inductors includes a top surface and a bottom surface opposite the top surface and that faces the first surface of the first circuit board. Each inductor is elevated above the first surface of the first circuit board such that at least a portion of the bottom surface of the inductor does not contact the first surface of the first circuit board. The first circuit board includes capacitors arranged in an area below the portion of the bottom surface of the inductor that does not contact the first surface of the first circuit board.
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公开(公告)号：US11552634B2
公开(公告)日：2023-01-10
申请号：US16921571
申请日：2020-07-06
Applicant: Google LLC
Inventor： Houle Gan , Mikhail Popovich , Shuai Jiang , Gregory Sizikov , Chee Yee Chung
IPC: H03K17/68 , H03K17/687 , G06F1/26 , H02M3/07
Abstract: An apparatus that includes an interposer, first power connectors that are disposed on a first surface and that receive respective power inputs from one or more power sources, second power connectors that are disposed on the second surface and that receive a respective third power connecter of an integrated circuit when the integrated circuit is mounted on the second surface of the interposer, a plurality of switches formed within the interposer, control circuitry formed within the interposer, and a sequencer circuit coupled to the control input of the control circuitry and that generates a different values for a control input signal that causes the control logic of the control circuitry to generate a corresponding set of switch signals, and the plurality of different values for the control input signal are generated according to a predefined sequence to provide power to the integrated circuit according to power up sequence.
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公开(公告)号：US20220269297A1
公开(公告)日：2022-08-25
申请号：US17744025
申请日：2022-05-13
Applicant: Google LLC
Inventor： Robert Ashby Armistead, III , Shuai Jiang , Binayak Roy , Thomas James Norrie , Houle Gan
Abstract: A programmable thermal dissipation power (TDP) system with integrated circuits is provided. The programmable TDP system includes a software interface, a monitoring circuit, and a controller circuit. The monitoring circuit may provide for the instantaneous input power supplied to the system. The controller circuit may monitor both the target TDP information specified from upstream and the input power readings. The controller circuit may generate a pulse-width modulation (PWM) signal that corresponds to a gap between the two power levels and sends the signal to the integrated circuits on the system. The integrated circuit may respond to the change in the input PWM signal and may adjust its power consumption. For example, the integrated circuit may adjust the clock frequency, adjust the instruction rate, skip a number of clock cycles, etc.
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Patent Agency Ranking
公开(公告)号：US11334103B2
公开(公告)日：2022-05-17
申请号：US16996405
申请日：2020-08-18
Applicant: Google LLC
Inventor： Robert Ashby Armistead, III , Shuai Jiang , Binayak Roy , Thomas James Norrie , Houle Gan
Abstract: A programmable thermal dissipation power (TDP) system with integrated circuits is provided. The programmable TDP system includes a software interface, a monitoring circuit, and a controller circuit. The monitoring circuit may provide for the instantaneous input power supplied to the system. The controller circuit may monitor both the target TDP information specified from upstream and the input power readings. The controller circuit may generate a pulse-width modulation (PWM) signal that corresponds to a gap between the two power levels and sends the signal to the integrated circuits on the system. The integrated circuit may respond to the change in the input PWM signal and may adjust its power consumption. For example, the integrated circuit may adjust the clock frequency, adjust the instruction rate, skip a number of clock cycles, etc.
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公开(公告)号：US10985652B1
公开(公告)日：2021-04-20
申请号：US16806521
申请日：2020-03-02
Applicant: Google LLC
Inventor： Shuai Jiang , Gregory Sizikov , Mikhail Popovich
Abstract: This disclosure relates to power balancer circuits that enable multiple load zones of an IC to be powered in series while maintaining balanced voltage at each load zone. In one aspect, a circuit includes load zones that are powered in series. The circuit includes a power balancer for balancing a voltage across each load zone. The power balancer includes an equivalent DC transformer array that includes, for each load zone, an equivalent DC transformer connected in parallel with the load zone. The power balancer includes, for each load zone, a bus capacitor connected in parallel with the load zone. Each equivalent DC transformer is electrically connected to each other equivalent DC transformer providing an electrical path for each bus capacitor to discharge current to each other bus capacitor when a voltage across a bus capacitor is greater than a voltage across another bus capacitor.
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公开(公告)号：US10742211B1
公开(公告)日：2020-08-11
申请号：US16527569
申请日：2019-07-31
Applicant: Google LLC
Inventor： Houle Gan , Mikhail Popovich , Shuai Jiang , Gregory Sizikov , Chee Yee Chung
IPC: H01L25/00 , H03K17/687 , G06F1/26 , H02M3/07
Abstract: An apparatus that includes an interposer, first power connectors that are disposed on a first surface and that receive respective power inputs from one or more power sources, second power connectors that are disposed on the second surface and that receive a respective third power connector of an integrated circuit when the integrated circuit is mounted on the second surface of the interposer, a plurality of switches formed within the interposer, control circuitry formed within the interposer, and a sequencer circuit coupled to the control input of the control circuitry and that generates a different values for a control input signal that causes the control logic of the control circuitry to generate a corresponding set of switch signals, and the plurality of different values for the control input signal are generated according to a predefined sequence to provide power to the integrated circuit according to power up sequence.
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公开(公告)号：US10211733B1
公开(公告)日：2019-02-19
申请号：US15796488
申请日：2017-10-27
Applicant: Google LLC
Inventor： Shuai Jiang , Xin Li
Abstract: An apparatus that includes a resonant DC-DC converter with switching frequencies based on stray inductances of the physical components used to construct the apparatus. This results in a relatively high efficiency and high density DC-DC converter that, in some implementations, does not require a discrete inductor component.
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公开(公告)号：US20180239602A1
公开(公告)日：2018-08-23
申请号：US15956716
申请日：2018-04-18
Applicant: Google LLC
Inventor： Tal Dayan , Safa Alai , Arda Atali , Shuai Jiang
CPC classification number: G06F8/71 , G06F8/70 , G06F9/44505
Abstract: Disclosed are apparatus and methods for processing configuration data sets. A computing device can retrieve configuration data set(s) from data storage. A configuration data set can include key-value pairs related to configuring a software application, where a key-value pair can include a key name and an associated value. The computing device can merge the configuration data set(s) into a merged configuration data set by at least: determining whether multiple key-value pairs of the configuration data set(s) are in conflict; after determining that multiple key-value pairs of the configuration data set(s) are in conflict, determining a representative key-value pair to represent the multiple key-value pairs; and adding the representative key-value pair to the merged configuration data set. The computing device can provide the merged configuration data set to the software application.
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