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11.发明申请Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores 有权基于建筑级吞吐量的功率建模方法和设备，用于普及时钟门控处理器内核公开(公告)号：US20060080625A1
公开(公告)日：2006-04-13
申请号：US10960730
申请日：2004-10-07
申请人： Pradip Bose , Tejas Karkhanis , Srinivasan Ramani , Malcolm Ware , Ken Vu
发明人： Pradip Bose , Tejas Karkhanis , Srinivasan Ramani , Malcolm Ware , Ken Vu
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A method, system, and apparatus for estimating the power dissipated by a processor core processing a workload, where the method includes analyzing a reference test case to generate a reference workload characteristic. Analyzing an actual workload to generate an actual workload characteristic. Performing a power analysis for the reference test case to establish a reference power dissipation value. Estimating an actual workload power dissipation value responsive to the actual and reference workload characteristics and the reference power dissipation value
摘要翻译： 一种用于估计由处理器核心处理工作负载消耗的功率的方法，系统和装置，其中所述方法包括分析参考测试用例以生成参考工作负载特性。 分析实际工作负载以生成实际工作负载特性。 对参考测试用例进行功率分析，建立参考功耗值。 根据实际和参考工作负载特性以及参考功耗值估算实际工作负载功耗值
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12.发明申请Architectural Level Throughput Based Power Modeling Methodology and Apparatus for Pervasively Clock-Gated Processor Cores 有权基于建筑级吞吐量的电力建模方法和设备，用于普适时钟门控处理器内核公开(公告)号：US20080027664A1
公开(公告)日：2008-01-31
申请号：US11780712
申请日：2007-07-20
申请人： Pradip Bose , Tejas Karkhanis , Srinivasan Ramani , Malcolm Ware , Ken Vu
发明人： Pradip Bose , Tejas Karkhanis , Srinivasan Ramani , Malcolm Ware , Ken Vu
IPC分类号： G01R21/00
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A method for estimating power dissipated by a processor core processing a workload-includes analyzing a reference test case to generate a reference workload characteristic, analyzing an actual workload to generate an actual workload characteristic, performing a power analysis for the reference test case to establish a reference power dissipation value and estimating an actual workload power dissipation value responsive to the actual and reference workload characteristics and the reference power dissipation value.
摘要翻译： 一种用于估计由处理器核心处理工作负载的功率消耗的方法 - 包括分析参考测试用例以生成参考工作负载特征，分析实际工作负载以产生实际工作负载特性，对参考测试用例执行功率分析以建立 参考功耗值，并根据实际和参考工作负载特性和参考功耗值估计实际工作负载功耗值。
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公开(公告)号：US20050185581A1
公开(公告)日：2005-08-25
申请号：US10782617
申请日：2004-02-19
申请人： Jeffrey Bradford , Gordon Davis , Dongming Hwang , Clark Jeffries , Srinivasan Ramani , Kartik Sudeep , Ken Vu
发明人： Jeffrey Bradford , Gordon Davis , Dongming Hwang , Clark Jeffries , Srinivasan Ramani , Kartik Sudeep , Ken Vu
CPC分类号： H04L47/10 , H04L47/29 , H04L47/323
摘要： The present invention provides for a computer network method and system that applies “hysteresis” to an active queue management algorithm. If a queue is at a level below a certain low threshold and a burst of packets arrives at a network node, then the probability of dropping the initial packets in the burst is recalculated, but the packets are not dropped. However, if the queue level crosses beyond a hysteresis threshold, then packets are discarded pursuant to a drop probability. Also, according to the present invention, queue level may be decreased until it becomes less than the hysteresis threshold, with packets dropped per the drop probability until the queue level decreases to at least a low threshold. In one embodiment, an adaptive algorithm is also provided to adjust the transmit probability for each flow together with hysteresis to increase the packet transmit rates to absorb bursty traffic.
摘要翻译： 本发明提供一种向活动队列管理算法应用“迟滞”的计算机网络方法和系统。 如果队列处于低于某个低阈值的水平，并且一群数据包到达网络节点，则重新计算突发中丢弃初始数据包的概率，但不会丢弃数据包。 然而，如果队列级别超过滞后阈值，则根据丢弃概率丢弃数据包。 此外，根据本发明，可以减少队列级别，直到其变得小于滞后阈值，其中每个丢弃概率的分组丢弃，直到队列级别降低到至少低阈值。 在一个实施例中，还提供自适应算法来调整每个流的发送概率以及迟滞以增加分组传输速率以吸收突发业务。
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公开(公告)号：US10102439B2
公开(公告)日：2018-10-16
申请号：US12349311
申请日：2009-01-06
申请人： Srinivasan Ramani , Badri Narayanan Ranganathan , Srinivasu Godavari , Anjaneyulu Seetha Rama Kuchibhotla , Nagabhushana Ayyanahalli Matad
发明人： Srinivasan Ramani , Badri Narayanan Ranganathan , Srinivasu Godavari , Anjaneyulu Seetha Rama Kuchibhotla , Nagabhushana Ayyanahalli Matad
IPC分类号： G06Q20/12 , G06K9/20 , G07D7/0047
摘要： A method of and system for verifying a document, the method comprising generating verification information for the document, comparing the verification information with authentic verification information, and identifying differences between the document and an authentic document.
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公开(公告)号：US08238665B2
公开(公告)日：2012-08-07
申请号：US12358260
申请日：2009-01-23
IPC分类号： G06K9/34
CPC分类号： H04N1/00002 , H04N1/00029 , H04N1/00037 , H04N1/00047 , H04N1/00087 , H04N1/0009 , H04N1/00092 , H04N1/00816 , H04N2201/04717
摘要： A document processing method comprises adding document markers to predetermined locations of an electronically stored document. These are printed with the document. The document is scanned and the scanned document markers are used to process the scanned image. This processing comprises at least pixel threshold setting, and determination of the locations of the scanned image which are to be processed to derive the pixels of a digital version of the document. This enables local deformations in the paper document to be corrected, and enables correct thresholds for the printing and scanning operations to be applied. The electronically stored document can be processed to derive a set of document properties which can be used when constructing the digital version.
摘要翻译： 文件处理方法包括将文档标记添加到电子存储文档的预定位置。 这些打印文档。 扫描文档，并使用扫描的文档标记来处理扫描图像。 该处理至少包括像素阈值设置以及要处理的扫描图像的位置的确定以导出文档的数字版本的像素。 这使得纸张文档中的局部变形被校正，并且使得能够应用用于打印和扫描操作的正确的阈值。 可以处理电子存储的文档以导出在构建数字版本时可以使用的一组文档属性。
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公开(公告)号：US20120197991A1
公开(公告)日：2012-08-02
申请号：US13338960
申请日：2011-12-28
IPC分类号： G06F15/16
摘要： Intuitive interaction may be performed over a network. The interaction may include collection of feedback from participants, wherein the feedback is active, passive, or a combination of both. The feedback from the participants may be aggregated and the aggregated feedback can be provided to at least one participant or a non-participant.
摘要翻译： 可以通过网络执行直观的交互。 交互可以包括来自参与者的反馈的收集，其中反馈是主动的，被动的或两者的组合。 可以聚合来自参与者的反馈，并且可以向至少一个参与者或非参与者提供聚合反馈。
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公开(公告)号：US08194976B2
公开(公告)日：2012-06-05
申请号：US12234720
申请日：2008-09-22
申请人： Anil Kumar , Srinivasan Ramani , Darpan Goel
发明人： Anil Kumar , Srinivasan Ramani , Darpan Goel
IPC分类号： G06K9/36
CPC分类号： G06K19/06037 , G06K7/1434 , G06K19/06056
摘要： A method of independently encoding an image with two information channels comprises generating an image which encodes a primary information channel based on brightness levels. The image is modified to encode a secondary information channel. This image modification comprises applying one of two image output values to the image portion, wherein the brightness of a modified image portion is not changed such as to change the primary information channel encoding.
摘要翻译： 利用两个信息信道独立地编码图像的方法包括：基于亮度级产生对主信息信道进行编码的图像。 修改图像以对次要信息信道进行编码。 该图像修改包括将两个图像输出值中的一个应用于图像部分，其中修改的图像部分的亮度不改变，以改变主信息信道编码。
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18.发明授权公开(公告)号：US08589922B2
公开(公告)日：2013-11-19
申请号：US12900992
申请日：2010-10-08
IPC分类号： G06F9/455
CPC分类号： G06F9/45558 , G06F2009/45591
摘要： A number of hypervisor register fields are set to specify which processor cores are allowed to generate a number of performance events for a particular thread group. A plurality of threads for an application running in the computing environment to a plurality of thread groups are configured by a plurality of thread group fields in a plurality of control registers. A number of counter sets are allowed to count a number of thread group events originating from one of a shared resource and a shared cache are specified by a number of additional hypervisor register fields.
摘要翻译： 设置了一些管理程序注册字段，以指定允许哪些处理器核心为特定线程组生成多个性能事件。 用于在计算环境中运行到多个线程组的应用的多个线程由多个控制寄存器中的多个线程组字段配置。 允许多个计数器组对由共享资源中的一个发起的线程组事件的数量进行计数，并且共享高速缓存由多个额外的管理程序寄存器字段指定。
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19.发明授权Sharing sampled instruction address registers for efficient instruction sampling in massively multithreaded processors 失效共享采样指令地址寄存器，用于大规模多线程处理器中的高效指令采样公开(公告)号：US08489787B2
公开(公告)日：2013-07-16
申请号：US12902491
申请日：2010-10-12
IPC分类号： G06F13/24
CPC分类号： G06F11/3404 , G06F11/3466 , G06F2201/865 , G06F2201/88
摘要： Sampled instruction address registers are shared among multiple threads executing on a plurality of processor cores. Each of a plurality of sampled instruction address registers are assigned to a particular thread running for an application on the plurality of processor cores. Each of the sampled instruction address registers are configured by storing in each of the sampled instruction address registers a thread identification of the particular thread in a thread identification field and a processor identification of a particular processor on which the particular thread is running in a processor identification field.
摘要翻译： 采样指令地址寄存器在多个处理器核心上执行的多个线程之间共享。 将多个采样指令地址寄存器中的每一个分配给在多个处理器核上为应用程序运行的特定线程。 每个采样指令地址寄存器通过在每个采样指令地址寄存器中存储线程标识字段中的特定线程的线程标识和特定线程在其上运行的处理器标识中的处理器标识来配置 领域。
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公开(公告)号：US20110191603A1
公开(公告)日：2011-08-04
申请号：US12700513
申请日：2010-02-04
IPC分类号： G06F1/00
CPC分类号： G06F1/00 , Y02D10/124
摘要： A system for controlling a multitasking microprocessor system includes an interconnect, a plurality of processing units connected to the interconnect forming a single-source, single-sink flow network, wherein the plurality of processing units pass data between one another from the single-source to the single-sink, and a monitor connected to the interconnect for monitoring a portion of a resource consumed by each of the plurality of processing units and for controlling the plurality of processing units according to a predetermined budget for the resource to control a data overflow condition, wherein the monitor controls performance and power modes of the plurality of processing units.
摘要翻译： 用于控制多任务微处理器系统的系统包括互连，连接到形成单源单一信宿流网络的互连的多个处理单元，其中所述多个处理单元将数据从单一源传递到 所述单个接收器和连接到所述互连的监视器，用于监视所述多个处理单元中的每一个所消耗的资源的一部分，并且用于根据所述资源的预定预算控制所述多个处理单元以控制数据溢出条件 ，其中所述监视器控制所述多个处理单元的性能和功率模式。
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