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    Active flow management with hysteresis
    11.
    发明申请
    Active flow management with hysteresis 失效
    主动流量管理带滞后

    公开(公告)号：US20050185581A1

    公开(公告)日：2005-08-25

    申请号：US10782617

    申请日：2004-02-19

    申请人： Jeffrey Bradford ,  Gordon Davis ,  Dongming Hwang ,  Clark Jeffries ,  Srinivasan Ramani ,  Kartik Sudeep ,  Ken Vu

    发明人： Jeffrey Bradford ,  Gordon Davis ,  Dongming Hwang ,  Clark Jeffries ,  Srinivasan Ramani ,  Kartik Sudeep ,  Ken Vu

    IPC分类号： H04L12/56 ,  H04J3/16

    CPC分类号： H04L47/10 ,  H04L47/29 ,  H04L47/323

    摘要： The present invention provides for a computer network method and system that applies “hysteresis” to an active queue management algorithm. If a queue is at a level below a certain low threshold and a burst of packets arrives at a network node, then the probability of dropping the initial packets in the burst is recalculated, but the packets are not dropped. However, if the queue level crosses beyond a hysteresis threshold, then packets are discarded pursuant to a drop probability. Also, according to the present invention, queue level may be decreased until it becomes less than the hysteresis threshold, with packets dropped per the drop probability until the queue level decreases to at least a low threshold. In one embodiment, an adaptive algorithm is also provided to adjust the transmit probability for each flow together with hysteresis to increase the packet transmit rates to absorb bursty traffic.

    摘要翻译： 本发明提供一种向活动队列管理算法应用“迟滞”的计算机网络方法和系统。 如果队列处于低于某个低阈值的水平，并且一​​群数据包到达网络节点，则重新计算突发中丢弃初始数据包的概率，但不会丢弃数据包。 然而，如果队列级别超过滞后阈值，则根据丢弃概率丢弃数据包。 此外，根据本发明，可以减少队列级别，直到其变得小于滞后阈值，其中每个丢弃概率的分组丢弃，直到队列级别降低到至少低阈值。 在一个实施例中，还提供自适应算法来调整每个流的发送概率以及迟滞以增加分组传输速率以吸收突发业务。

    Prefetch mechanism based on page table attributes
    12.
    发明申请
    Prefetch mechanism based on page table attributes 有权
    基于页表属性的预取机制

    公开(公告)号：US20060265552A1

    公开(公告)日：2006-11-23

    申请号：US11131582

    申请日：2005-05-18

    申请人： Gordon Davis ,  Thomas Genduso ,  Harold Kossman ,  Robert Todd

    发明人： Gordon Davis ,  Thomas Genduso ,  Harold Kossman ,  Robert Todd

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0862 ,  G06F12/10 ,  G06F12/1027 ,  G06F2212/6024 ,  G06F2212/6026

    摘要： A prefetch mechanism using prefetch attributes is disclosed. In one aspect, an explicit request for data stored in a memory is provided, and a prefetch attribute in a page table entry associated with the explicit request is examined to determine whether to provide one or more prefetch requests based on the prefetch attribute. Another aspect includes determining dynamic prefetch attributes for use in prefetching data, in which prefetch attributes are adjusted based on memory access requests that target next sequential blocks of memory relative to the most recent previous access in a page of memory.

    摘要翻译： 公开了一种使用预取属性的预取机制。 在一个方面，提供对存储在存储器中的数据的显式请求，并且检查与显式请求相关联的页表条目中的预取属性，以基于预取属性来确定是否提供一个或多个预取请求。 另一方面包括确定用于在预取数据中使用的动态预取属性，其中基于存储器访问请求来调整预取属性，所述存储器访问请求相对于存储器页面中最近的先前存取的下一个顺序存储块。

    Facilitating inter-DSP data communications
    14.
    发明申请
    Facilitating inter-DSP data communications 失效
    促进DSP间数据通信

    公开(公告)号：US20050188129A1

    公开(公告)日：2005-08-25

    申请号：US10783757

    申请日：2004-02-20

    申请人： Youseff Abdelilah ,  Bartholomew Blaner ,  Gordon Davis ,  Jeffrey Derby ,  Joseph Garvey ,  Malcolm Ware ,  Hua Ye

    发明人： Youseff Abdelilah ,  Bartholomew Blaner ,  Gordon Davis ,  Jeffrey Derby ,  Joseph Garvey ,  Malcolm Ware ,  Hua Ye

    IPC分类号： G06F3/00 ,  G06F13/28 ,  H04L29/06

    CPC分类号： G06F13/28

    摘要： A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.

    摘要翻译： 一种用于促进数字间数字信号处理（DSP）数据通信的方法，计算机程序产品和系统。 直接存储器访问（DMA）控制器可以被配置为便于在耦合到DMA控制器的第一和第二DSP处理器核之间传输数据。 DMA控制器可以读取被称为“缓冲器描述符块”的数据结构来执行数据传送。 缓冲器描述符块可以存储指示要检索和存储数据的源地址和目的地址。 缓冲器描述符块还可以存储指示要传送的数据的大小的值，例如字节数。 然后，DMA控制器可以将位于第一DSP处理器核心中的源地址处的数据以从缓冲器描述符块指示的大小（例如，字节数）传送到第二DSP处理器核心中的目的地地址。

    DRAM access command queuing structure
    16.
    发明申请
    DRAM access command queuing structure 有权
    DRAM访问命令排队结构

    公开(公告)号：US20060026342A1

    公开(公告)日：2006-02-02

    申请号：US10899937

    申请日：2004-07-27

    申请人： Jean Calvignac ,  Chih-Jen Chang ,  Gordon Davis ,  Fabrice Verplanken

    发明人： Jean Calvignac ,  Chih-Jen Chang ,  Gordon Davis ,  Fabrice Verplanken

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1642

    摘要： Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing dead cycles. The arbiter first divides DRAM accesses into write accesses and read accesses. The access requests are divided into accesses per memory bank with a threshold limit imposed on the number of accesses to each memory bank. The write receive packets are rotated among the banks based on the write queue status. The status of the write queue for each memory bank may also be used for system flow control. The arbiter also typically includes the ability to determine access windows based on the status of the command queues, and to perform arbitration on each access window.

    摘要翻译： 访问仲裁器被用于将对DRAM存储器件，特别是快速循环DRAM中的各个存储体的读取和写入访问请求进行优先级排序。 这用于通过避免对同一存储体的连续访问并且通过最小化死循环来优化用于读取和写入操作的存储器带宽。 仲裁器首先将DRAM访问划分为写访问和读访问。 访问请求被划分为每个存储体的访问，并且对每个存储体的访问次数施加了阈值限制。 基于写入队列状态，写入接收数据包在存储体之间旋转。 每个存储体的写入队列的状态也可以用于系统流控制。 仲裁器还通常包括基于命令队列的状态来确定访问窗口的能力，并且在每个访问窗口上执行仲裁。

    Performance of a cache by including a tag that stores an indication of a previously requested address by the processor not stored in the cache
    17.
    发明申请
    Performance of a cache by including a tag that stores an indication of a previously requested address by the processor not stored in the cache 失效
    缓存的性能包括一个标签，该标签存储未存储在高速缓存中的处理器先前请求的地址的指示

    公开(公告)号：US20050080995A1

    公开(公告)日：2005-04-14

    申请号：US10685054

    申请日：2003-10-14

    申请人： Gordon Davis ,  Thomas Genduso

    发明人： Gordon Davis ,  Thomas Genduso

    IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/12

    CPC分类号： G06F12/126

    摘要： A method and system for improving the performance of a cache. The cache may include a tag entry that identifies the previously requested address by the processor whose data was not located in the cache. If the processor requests that address a second time, then there is a significant probability that the address will be accessed again. When the processor requests the address identified by the tag entry a second time, the cache is updated by inserting the data located at that address and evicting the data located in the least recently used entry. In this manner, data will not be evicted from the cache unless there is a significant probability that the data placed in the cache will likely be accessed again. Hence, data may not be evicted in the cache by the processor and replaced with data that will not be reused, such as in an interrupt routine.

    摘要翻译： 一种用于提高缓存性能的方法和系统。 缓存可以包括标识条目，其标识由数据未位于高速缓存中的处理器先前请求的地址。 如果处理器第二次请求该地址，则重新有可能再次访问该地址。 当处理器第二次请求由标签条目标识的地址时，通过插入位于该地址的数据并驱逐位于最近最少使用的条目中的数据来更新高速缓存。 以这种方式，除非存在可能再次访问缓存中的数据的重大概率，否则数据将不会从高速缓存中逐出。 因此，数据可能不会被处理器在高速缓存中驱逐，并且被替换为不被重用的数据，例如在中断程序中。

    Facilitating Inter-DSP Data Communications
    18.
    发明申请
    Facilitating Inter-DSP Data Communications 审中-公开

    公开(公告)号：US20080010390A1

    公开(公告)日：2008-01-10

    申请号：US11856509

    申请日：2007-09-17

    申请人： Youseff Abdelilah ,  Bartholomew Blaner ,  Gordon Davis ,  Jeffrey Derby ,  Joseph Garvey ,  Malcolm Ware ,  Hua Ye

    发明人： Youseff Abdelilah ,  Bartholomew Blaner ,  Gordon Davis ,  Jeffrey Derby ,  Joseph Garvey ,  Malcolm Ware ,  Hua Ye

    IPC分类号： G06F3/00

    CPC分类号： G06F13/28

    摘要： A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.

    Method and apparatus for translating a virtual address to a real address using blocks of contiguous page table entries
    19.
    发明申请
    Method and apparatus for translating a virtual address to a real address using blocks of contiguous page table entries 有权
    使用连续页表项的块将虚拟地址翻译成实地址的方法和装置

    公开(公告)号：US20070079106A1

    公开(公告)日：2007-04-05

    申请号：US11232773

    申请日：2005-09-22

    申请人： Gordon Davis

    发明人： Gordon Davis

    IPC分类号： G06F12/00 ,  G06F7/00

    CPC分类号： G06F12/1018 ,  G06F2212/1044

    摘要： A page table mechanism translates virtual addresses to real addresses. In a first aspect, page table entries are contained in equal-sized blocks, the entries within each block corresponding to contiguous pages of virtual address space. Preferably, the common high-order portion of the virtual address is contained in segments distributed among multiple page table entries of the block. In a second aspect, the virtual address indexes a binary tree definitional structure. Decode logic traverses a binary tree defined by the definitional structure by testing selective bits of the virtual address to reach a leaf of the binary tree, which defines the location of data defining the real address.

    摘要翻译： 页表机制将虚拟地址转换为实际地址。 在第一方面，页表条目包含在等大小的块中，每个块内的条目对应于虚拟地址空间的连续页面。 优选地，虚拟地址的公共高阶部分包含在分块在块的多个表表项之间的段中。 在第二方面，虚拟地址索引二进制树定义结构。 解码逻辑遍历由定义结构定义的二叉树，通过测试虚拟地址的选择性位以到达二叉树的叶，该二叉树定义了定义实际地址的数据的位置。

    System and method for exchanging messages in a multi-processor environment
    20.
    发明申请
    System and method for exchanging messages in a multi-processor environment 失效
    用于在多处理器环境中交换消息的系统和方法

    公开(公告)号：US20070033303A1

    公开(公告)日：2007-02-08

    申请号：US11198042

    申请日：2005-08-05

    申请人： Jeffrey Bridges ,  Gordon Davis ,  Thomas Sartorius ,  Michael Siegel

    发明人： Jeffrey Bridges ,  Gordon Davis ,  Thomas Sartorius ,  Michael Siegel

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： A method and system for messaging between processors and co-processors connected through a bus. The method permits a multi-thread system processor to request the services of a processor or co-processor located on the bus. Message control blocks are stored in a memory which identify the physical address of the target processor, as well as a memory location in the memory dedicated to the thread requesting the service. When the system processor requests service of a processor or co-processor, a DCR command is created pointing to the message control block. A message is built from information contained in the message control block or transferred to the processor or co-processor. The return address for the processor or co-processor message is concatenated with the thread number, so that the processor or co-processor can create a return message specifically identifying memory space dedicated to the requesting thread for storage of the response message.

    摘要翻译： 用于通过总线连接的处理器和协处理器之间的消息传递的方法和系统。 该方法允许多线程系统处理器请求位于总线上的处理器或协处理器的服务。 消息控制块存储在识别目标处理器的物理地址的存储器中，以及专用于请求服务的线程的存储器中的存储器位置。 当系统处理器请求处理器或协处理器的服务时，创建指向消息控制块的DCR命令。 消息由消息控制块中包含的信息构建或传送到处理器或协处理器。 处理器或协处理器消息的返回地址与线程号连接，使得处理器或协处理器可以创建专用于识别请求线程的存储空间的返回消息以存储响应消息。