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11.发明授权Method and apparatus for reducing host overhead in a socket server implementation 有权减少套接字服务器实现中的主机开销的方法和装置公开(公告)号：US07930349B2
公开(公告)日：2011-04-19
申请号：US12574263
申请日：2009-10-06
IPC分类号： G06F15/16
CPC分类号： H04L69/16 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9063 , H04L69/162 , H04L69/163 , H04L69/165
摘要： A network application executing on a host system provides a list of application buffers in host memory stored in a queue to a network services processor coupled to the host system. The application buffers are used for storing data transferred on a socket established between the network application and a remote network application executing in a remote host system. Using the application buffers, data received by the network services processor over the network is transferred between the network services processor and the application buffers. After the transfer, a completion notification is written to one of the two control queues in the host system. The completion notification includes the size of the data transferred and an identifier associated with the socket. The identifier identifies a thread associated with the transferred data and the location of the data in the host system.
摘要翻译： 在主机系统上执行的网络应用程序将存储在队列中的主机存储器中的应用缓冲器列表提供给耦合到主机系统的网络服务处理器。 应用程序缓冲区用于存储在网络应用程序和在远程主机系统中执行的远程网络应用程序之间建立的套接字上传输的数据。 使用应用缓冲器，由网络服务处理器通过网络接收的数据在网络服务处理器和应用缓冲器之间传送。 在传输之后，将完成通知写入主机系统中的两个控制队列之一。 完成通知包括传输的数据的大小和与套接字相关联的标识符。 标识符标识与传送的数据相关联的线程和主机系统中数据的位置。
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12.发明授权Method and apparatus for reducing host overhead in a socket server implementation 有权减少套接字服务器实现中的主机开销的方法和装置公开(公告)号：US07613813B2
公开(公告)日：2009-11-03
申请号：US11225373
申请日：2005-09-12
IPC分类号： G06F15/16
CPC分类号： H04L69/16 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9063 , H04L69/162 , H04L69/163 , H04L69/165
摘要： A network application executing on a host system provides a list of application buffers in host memory stored in a queue to a network services processor coupled to the host system. The application buffers are used for storing data transferred on a socket established between the network application and a remote network application executing in a remote host system. Using the application buffers, data received by the network services processor over the network is transferred between the network services processor and the application buffers. After the transfer, a completion notification is written to one of the two control queues in the host system. The completion notification includes the size of the data transferred and an identifier associated with the socket. The identifier identifies a thread associated with the transferred data and the location of the data in the host system.
摘要翻译： 在主机系统上执行的网络应用程序将存储在队列中的主机存储器中的应用缓冲器列表提供给耦合到主机系统的网络服务处理器。 应用程序缓冲区用于存储在网络应用程序和在远程主机系统中执行的远程网络应用程序之间建立的套接字上传输的数据。 使用应用缓冲器，由网络服务处理器通过网络接收的数据在网络服务处理器和应用缓冲器之间传送。 在传输之后，将完成通知写入主机系统中的两个控制队列之一。 完成通知包括传输的数据的大小和与套接字相关联的标识符。 标识符标识与传送的数据相关联的线程和主机系统中数据的位置。
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13.发明授权System and method to provide non-coherent access to a coherent memory system 有权提供对相干存储器系统的非相干访问的系统和方法公开(公告)号：US08850125B2
公开(公告)日：2014-09-30
申请号：US13280756
申请日：2011-10-25
CPC分类号： G06F12/0888 , G06F12/08 , G06F12/0831
摘要： In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.
摘要翻译： 在一个实施例中，系统包括存储器和存储器控制器，其提供到存储器的高速缓存访问路径和到存储器的旁路高速缓存访问路径，接收从旁路高速缓存访问路径上的存储器读取图形数据的请求，以及 接收从缓存访问路径上的内存中读取非图形数据的请求。 一种方法包括在存储器控制器处接收来自旁路高速缓存访问路径上的存储器的图形数据的请求，在存储器控制器处接收请求以通过高速缓存访问路径从存储器读取非图形数据， 在内存控制器中，在使用仲裁的请求中。
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公开(公告)号：US07024533B2
公开(公告)日：2006-04-04
申请号：US10441451
申请日：2003-05-20
申请人： Richard E. Kessler , Peter J. Bannon , Maurice B. Steinman , Scott E. Breach , Allen J. Baum , Gregg A. Bouchard
发明人： Richard E. Kessler , Peter J. Bannon , Maurice B. Steinman , Scott E. Breach , Allen J. Baum , Gregg A. Bouchard
IPC分类号： G06F12/00
CPC分类号： G06F13/1689
摘要： A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller preferably includes a channel interface and synchronization logic circuit for each memory channel. This circuit includes read and write buffers and load and unload pointers for the read buffer. Unload pointer logic generates the unload pointer and load pointer logic generates the load pointer. The pointers preferably are free-running pointers that increment in accordance with two different clock signals. The load pointer increments in accordance with a clock generated by the memory controller but that has been routed out to and back from the memory modules. The unload pointer increments in accordance with a clock generated by the computer system itself Because the trace length of each memory channel may differ, the time that it takes for a memory module to provide read data back to the memory controller may differ for each channel. The “skew” is defined as the difference in time between when the data arrives on the earliest channel and when data arrives on the latest channel. During system initialization, the pointers are synchronized. After initialization, the pointers are used to load and unload the read buffers in such a way that the effects of inner-channel skew is eliminated.
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15.发明授权公开(公告)号：US06636955B1
公开(公告)日：2003-10-21
申请号：US09652480
申请日：2000-08-31
申请人： Richard E. Kessler , Peter J. Bannon , Maurice B. Steinman , Scott E. Breach , Allen J. Baum , Gregg A. Bouchard
发明人： Richard E. Kessler , Peter J. Bannon , Maurice B. Steinman , Scott E. Breach , Allen J. Baum , Gregg A. Bouchard
IPC分类号： G06F1200
CPC分类号： G06F13/1689
摘要： A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller preferably includes a channel interface and synchronization logic circuit for each memory channel. This circuit includes read and write buffers and load and unload pointers for the read buffer. Unload pointer logic generates the unload pointer and load pointer logic generates the load pointer. The pointers preferably are free-running pointers that increment in accordance with two different clock signals. The load pointer increments in accordance with a clock generated by the memory controller but that has been routed out to and back from the memory modules. The unload pointer increments in accordance with a clock generated by the computer system itself. Because the trace length of each memory channel may differ, the time that it takes for a memory module to provide read data back to the memory controller may differ for each channel. The “skew” is defined as the difference in time between when the data arrives on the earliest channel and when data arrives on the latest channel. During system initialization, the pointers are synchronized. After initialization, the pointers are used to load and unload the read buffers in such a way that the effects of inner-channel skew is eliminated.
摘要翻译： 计算机系统具有存储器控制器，其包括耦合到多个存储器通道的读取缓冲器。 存储器控制器有利地消除由存储器模块位于与存储器控制器不同的距离处引起的通道间偏移。 存储器控制器优选地包括用于每个存储器通道的通道接口和同步逻辑电路。 该电路包括读取和写入缓冲区，读取缓冲区的加载和卸载指针。 卸载指针逻辑生成卸载指针，加载指针逻辑生成加载指针。 指针优选地是根据两个不同的时钟信号递增的自由运行指针。 负载指针根据由存储器控制器产生的时钟增加，但是已经被引出到存储器模块和从存储器模块返回。 卸载指针根据计算机系统本身产生的时钟增加。 因为每个存储器通道的迹线长度可能不同，所以存储器模块将读数据提供给存储器控制器所花费的时间可能对于每个通道而言可能不同。 “偏斜”被定义为数据到达最早通道时和数据到达最新通道之间的时间差。 在系统初始化期间，指针是同步的。 初始化之后，这些指针用于加载和卸载读取缓冲区，从而消除内部信道偏移的影响。
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公开(公告)号：US06754739B1
公开(公告)日：2004-06-22
申请号：US09651945
申请日：2000-08-31
IPC分类号： G06F1300
CPC分类号： G06F9/544
摘要： A method and architecture for improved system resource management and allocation for the processing of request and response messages in a computer system. The resource management scheme provides for dynamically sharing system resources, such as data buffers, between request and response messages or transactions. In particular, instead of simply dedicating a portion of the system resources to requests and the remaining portion to responses, a minimum amount of resources are reserved for responses and a minimum amount for requests, while the remaining resources are dynamically shared between both types of messages. The method and architecture of the present invention allows for more efficient use of system resources, while avoiding deadlock conditions and ensuring a minimum service rate for requests.
摘要翻译： 一种用于改进系统资源管理和分配以在计算机系统中处理请求和响应消息的方法和架构。 资源管理方案提供在请求和响应消息或事务之间动态共享系统资源，例如数据缓冲器。 特别地，不是简单地将系统资源的一部分专用于请求，而将余下的部分用于响应，而是为响应保留最小量的资源和用于请求的最小量，而剩余的资源在两种类型的消息之间动态共享 。 本发明的方法和体系结构允许更有效地利用系统资源，同时避免死锁状况并确保请求的最低服务速率。
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17.发明授权System and method to reduce memory access latencies using selective replication across multiple memory ports 有权使用多个内存端口选择性复制来减少内存访问延迟的系统和方法公开(公告)号：US08560757B2
公开(公告)日：2013-10-15
申请号：US13280738
申请日：2011-10-25
IPC分类号： G06F12/00
CPC分类号： G06F12/1018 , G06F12/0292 , G06F12/06 , G06F2212/174 , G06F2212/2532
摘要： In one embodiment, a system includes memory ports distributed into subsets identified by a subset index, where each memory port has an individual wait time based on a respective workload. The system further comprises a first address hashing unit configured to receive a read request including a virtual memory address associated with a replication factor and referring to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address referring to graph data in the memory ports within a subset indicated by the corresponding subset index. The system further comprises a memory replication controller configured to direct read requests to the hardware based address to the one of the memory ports within the subset indicated by the corresponding subset index with a lowest individual wait time.
摘要翻译： 在一个实施例中，系统包括分布到由子集索引识别的子集中的存储器端口，其中每个存储器端口基于相应的工作负载具有单独的等待时间。 该系统还包括第一地址哈希单元，其被配置为接收包括与复制因子相关联的虚拟存储器地址并参考图形数据的读取请求。 第一地址散列单元基于虚拟存储器地址将复制因子转换为相应的子集索引，并且参考由相应子集索引指示的子集内的存储器端口中的图形数据将虚拟存储器地址转换为基于硬件的存储器地址 。 该系统还包括存储器复制控制器，其被配置为将读取请求引导到基于硬件的地址到具有最低个人等待时间的相应子集索引指示的子集内的存储器端口之一。
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18.发明申请SYSTEM AND METHOD TO REDUCE MEMORY ACCESS LATENCIES USING SELECTIVE REPLICATION ACROSS MULTIPLE MEMORY PORTS 有权使用多个存储器端口选择性复制来减少存储器访问延迟的系统和方法公开(公告)号：US20130103904A1
公开(公告)日：2013-04-25
申请号：US13280738
申请日：2011-10-25
CPC分类号： G06F12/1018 , G06F12/0292 , G06F12/06 , G06F2212/174 , G06F2212/2532
摘要： In one embodiment, a system comprises multiple memory ports distributed into multiple subsets, each subset identified by a subset index and each memory port having an individual wait time. The system further comprises a first address hashing unit configured to receive a read request including a virtual memory address associated with a replication factor, and referring to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address that refers to graph data in the memory ports within a subset indicated by the corresponding subset index. The system further comprises a memory replication controller configured to direct read requests to the hardware based address to the one of the memory ports within the subset indicated by the corresponding subset index with a lowest individual wait time.
摘要翻译： 在一个实施例中，系统包括分布到多个子集中的多个存储器端口，每个子集由子集索引标识，每个存储器端口具有单独的等待时间。 该系统还包括第一地址哈希单元，其被配置为接收包括与复制因子相关联的虚拟存储器地址的读取请求，并且参考图形数据。 第一地址散列单元基于虚拟存储器地址将复制因子转换为对应的子集索引，并将虚拟存储器地址转换为基于硬件的存储器地址，该存储器地址涉及由相应子集指示的子集内的存储器端口中的图形数据 指数。 该系统还包括存储器复制控制器，其被配置为将读取请求引导到基于硬件的地址到具有最低个人等待时间的相应子集索引指示的子集内的存储器端口之一。
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19.发明授权Computer architecture and system for efficient management of bi-directional bus 有权用于双向总线高效管理的计算机架构和系统公开(公告)号：US06920512B2
公开(公告)日：2005-07-19
申请号：US10780395
申请日：2004-02-17
CPC分类号： G06F13/4059
摘要： An efficient system and method for managing reads and writes on a bi-directional bus to optimize bus performance while avoiding bus contention and avoiding read/write starvation. In particular, by intelligently managing reads and writes on a bi-directional bus, bus latency can be reduced while still ensuring no bus contention or read/write starvation. This is accomplished by utilizing bus streaming control logic, separate queues for reads and writes, and a simple 2 to 1 mux.
摘要翻译： 一种有效的系统和方法，用于管理双向总线上的读取和写入，以优化总线性能，同时避免总线争用并避免读取/写入饥饿。 特别地，通过智能地管理双向总线上的读取和写入，可以减少总线延迟，同时仍然确保没有总线争用或读取/写入饥饿。 这是通过利用总线流控制逻辑，单独的队列读取和写入以及简单的2到1多路复用来实现的。
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公开(公告)号：US06662265B1
公开(公告)日：2003-12-09
申请号：US09652704
申请日：2000-08-31
申请人： Richard E. Kessler , Maurice B. Steinman , Michael S. Bertone , Peter J. Bannon , Gregg A. Bouchard
发明人： Richard E. Kessler , Maurice B. Steinman , Michael S. Bertone , Peter J. Bannon , Gregg A. Bouchard
IPC分类号： G06F1200
CPC分类号： G06F12/0215 , G06F13/1631
摘要： A system and method is disclosed to track a large number of open pages in a computer memory system. The computer system contains one or more processors each including a memory controller containing a page table, the page table organized into a plurality of rows with each row able to store an address of an open memory page. A RIMM module containing RDRAM devices is coupled to each processor, each RDRAM containing a plurality of memory banks. The page table increases system memory performance by tracking a large number of open memory pages. Associated with the page table is a bank active table that indicates the memory banks in each RDRAM device having open memory pages. The page table enqueues accesses to the RIMM module in a precharge queue resulting from a page miss caused by the address of an open memory page occupying the same row of the page table as the address of the system memory access resulting in the page miss. The page table also enqueues accesses to system memory in a Row-address-select (“RAS”) queue resulting from a page miss caused by a row of the page table not containing any open memory page address. The page table enqueues accesses to system memory resulting in page hits to open memory pages in a Column-address-select (“CAS”) queue. An entry in the precharge queue is then enqueued into the RAS queue. An entry in the RAS queue after completion is enqueued into the CAS Read or CAS Write queue.
摘要翻译： 公开了一种在计算机存储器系统中跟踪大量打开页面的系统和方法。 计算机系统包含一个或多个处理器，每个处理器包括包含页表的存储器控制器，所述页表被组织成多行，每行能够存储打开存储器页的地址。 包含RDRAM设备的RIMM模块耦合到每个处理器，每个RDRAM包含多个存储器组。 页面表通过跟踪大量的开放内存页面来增加系统内存性能。 与页表相关联的是一个存储区活动表，指示每个具有打开存储器页的RDRAM设备中的存储体。 页表格排队访问预充电队列中的RIMM模块，这是由于打开的内存页面的地址与页表的同一行的地址导致的页错误导致的系统内存访问的地址导致页错过。 页表还对由行页地址选择（“RAS”）队列访问系统内存进行排队，这是由于不包含任何打开的内存页地址的页表的行引起的页错误导致的。 页面表格对对系统内存的访问进行排队，导致页面命中，以打开列地址选择（“CAS”）队列中的内存页面。 然后将预充电队列中的条目排入RAS队列。 完成后RAS队列中的条目排入CAS读取或CAS写入队列。
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