公开(公告)号：US10509167B2

公开(公告)日：2019-12-17

申请号：US15959580

申请日：2018-04-23

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Amit S. Sharma ,  John Paul Strachan ,  Marco Fiorentino

IPC: G02B6/12

Abstract: Systems and methods are provided for processing an optical signal. An example system may include a source disposed on a substrate and capable of emitting the optical signal. A first waveguide is formed in the substrate to receive the optical signal. A first coupler is disposed on the substrate to receive a reflected portion of the optical signal. A second waveguide is formed in the substrate to receive the reflected portion from the first coupler. A second coupler is formed in the substrate to mix the optical signal and the reflected portion to form a mixed signal. Photodetectors are formed in the substrate to convert the mixed signal to an electrical signal. A processor is electrically coupled to the substrate and programmed to convert the electrical signal from a time domain to a frequency domain to determine a phase difference between the optical signal and the reflected portion.

公开(公告)号：US10146619B2

公开(公告)日：2018-12-04

申请号：US15320852

申请日：2014-07-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Erik Ordentlich ,  Amit S. Sharma

IPC: G11C29/00 ,  G06F11/10 ,  G11C8/10 ,  H03M13/13 ,  H03M13/29 ,  H03M13/00 ,  G06F3/06 ,  G11C7/10

Abstract: According to an example, a method for assigning redundancy in encoding data onto crossbar memory arrays is provided wherein each of said crossbar memory arrays include cells. The data may be allocated to a subset of the cells in multiple crossbar memory arrays. The redundancy for the data may then be assigned based on coordinates of the subset of cells within the multiple crossbar memory arrays onto which the data is allocated.

公开(公告)号：US20210225440A1

公开(公告)日：2021-07-22

申请号：US17223435

申请日：2021-04-06

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Amit S. Sharma ,  John Paul Strachan ,  Catherine Graves ,  Suhas Kumar ,  Craig Warner ,  Martin Foltin

IPC: G11C13/00 ,  G06N3/04 ,  G11C29/52 ,  G06F11/10

Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

公开(公告)号：US10984860B2

公开(公告)日：2021-04-20

申请号：US16364717

申请日：2019-03-26

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Amit S. Sharma ,  John Paul Strachan ,  Catherine Graves ,  Suhas Kumar ,  Craig Warner ,  Martin Foltin

IPC: G11C13/00 ,  G06F11/10 ,  G06N3/04 ,  G11C29/52

Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

公开(公告)号：US10930343B2

公开(公告)日：2021-02-23

申请号：US16107063

申请日：2018-08-21

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Amit S. Sharma ,  Suhas Kumar ,  Xia Sheng

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24 ,  G11C8/14

Abstract: A memristor device includes a first electrode, a second electrode, and a memristor layer disposed between the first electrode and the second electrode. The memristor layer is formed of a metal oxide. The memristor layer includes a plurality of regions that extend between the first electrode and the second electrode. The plurality of regions of the memristor layer are created with different concentrations of oxygen before electrical operation, and, during electrical operation, a voltage-conductance characteristic of the memristor device is controlled based on the different concentrations of oxygen of the plurality of regions. The controlling of the voltage-conductance characteristic includes increasing or decreasing the conductance of the memristor device toward a target conductance at a specific voltage.

公开(公告)号：US20200066340A1

公开(公告)日：2020-02-27

申请号：US16107063

申请日：2018-08-21

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Amit S. Sharma ,  Suhas Kumar ,  Xia Sheng

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00 ,  G11C8/14

Abstract: A memristor device includes a first electrode, a second electrode, and a memristor layer disposed between the first electrode and the second electrode. The memristor layer is formed of a metal oxide. The memristor layer includes a plurality of regions that extend between the first electrode and the second electrode. The plurality of regions of the memristor layer are created with different concentrations of oxygen before electrical operation, and, during electrical operation, a voltage-conductance characteristic of the memristor device is controlled based on the different concentrations of oxygen of the plurality of regions. The controlling of the voltage-conductance characteristic includes increasing or decreasing the conductance of the memristor device toward a target conductance at a specific voltage.

公开(公告)号：US20190324205A1

公开(公告)日：2019-10-24

申请号：US15959580

申请日：2018-04-23

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Amit S. Sharma ,  John Paul Strachan ,  Marco Fiorentino

IPC: G02B6/12

Abstract: Systems and methods are provided for processing an optical signal. An example system may include a source disposed on a substrate and capable of emitting the optical signal. A first waveguide is formed in the substrate to receive the optical signal. A first coupler is disposed on the substrate to receive a reflected portion of the optical signal. A second waveguide is formed in the substrate to receive the reflected portion from the first coupler. A second coupler is formed in the substrate to mix the optical signal and the reflected portion to form a mixed signal. Photodetectors are formed in the substrate to convert the mixed signal to an electrical signal. A processor is electrically coupled to the substrate and programmed to convert the electrical signal from a time domain to a frequency domain to determine a phase difference between the optical signal and the reflected portion.

公开(公告)号：US09767901B1

公开(公告)日：2017-09-19

申请号：US15245607

申请日：2016-08-24

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Amit S. Sharma ,  Gary Gibson ,  Naveen Muralimanohar ,  Martin Foltin ,  Greg Astfalk

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2213/15 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76

Abstract: An integrated circuit is provided. In an example, the integrated circuit includes a first address line, a selector device electrically coupled to the first address lines, and a memory device electrically coupled between the selector device and a second address line. The selector device has a first I-V response in a first current direction and a second I-V response in a second current direction that is different from the first I-V response.