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公开(公告)号：US11650751B2
公开(公告)日：2023-05-16
申请号：US16368981
申请日：2019-03-29
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Suhas Kumar , Thomas Van Vaerenbergh , John Paul Strachan
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679 , G06F17/11 , G06N10/00
Abstract: A method for determining a solution to a constrained optimization problem includes programming a weights matrix of a Hopfield network with a first encoded matrix representation of an initial constrained optimization problem. The method also includes employing the Hopfield network to determine a solution to the initial constrained optimization problem. Additionally, the method includes encoding a plurality of constrained optimization problems associated with a target constrained optimization problem into a plurality of encoded matrix representations each of which are a combination of the first and the second encoded matrix representations. The plurality of encoded matrix representations increases in convergence to the second encoded matrix representation of the target constrained optimization problem sequentially. The method further includes re-programming the weights matrix of the Hopfield network in an iterative manner with the plurality of encoded matrix representations.
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公开(公告)号：US11551056B2
公开(公告)日：2023-01-10
申请号：US16261398
申请日：2019-01-29
Applicant: Hewlett Packard Enterprise Development LP
Inventor： John Paul Strachan , Suhas Kumar , Thomas Van Vaerenbergh
Abstract: Staged neural networks and methods are described herein. In some embodiments, the methods may identify a plurality of second NP hard/complete problems that are similar to the first NP hard/complete problem and identify solutions to the second NP hard/complete problems. The methods may train a deep neural network with the second NP hard/complete problems and the solutions. The methods may provide the first NP hard/complete problem to the trained deep neural network to generate a preliminary solution to the first NP hard/complete problem and provide the preliminary solution to a recursive neural network configured to execute an energy minimization search. The recursive neural network may generate a final solution to the problem based on the preliminary solution.
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公开(公告)号：US10885430B2
公开(公告)日：2021-01-05
申请号：US15664058
申请日：2017-07-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Suhas Kumar
Abstract: A non-Boolean analog system includes a first Mott memristor having a first value of a characteristic, and a second Mott memristor having a second value of the characteristic different than the first value. The system includes a resistance in series with the first and second Mott memristors to form a network having a capacitance and that is operable as a relaxation oscillator. Responsive to electrical excitation, a temperature of the network operating an environment including ambient thermal noise settles at an equilibrium corresponding to a global minimum that is a maximally optimal global solution to a global optimization problem to which the network corresponds.
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公开(公告)号：US20200218967A1
公开(公告)日：2020-07-09
申请号：US16371230
申请日：2019-04-01
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： John Paul Strachan , Suhas Kumar
Abstract: A hardware accelerator including a crossbar array programmed to calculate node values of a neural network, the crossbar array comprising a plurality of row lines, a plurality of column lines, and a memory cell coupled between each combination of one row line and one column line. Also, an energy storing element disposed in the crossbar array between each combination of one row line and one column line and a filter that receives information from the energy storing element and provides new information for each node of the neural network.
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公开(公告)号：US10419346B1
公开(公告)日：2019-09-17
申请号：US15966719
申请日：2018-04-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： John Paul Strachan , Catherine Graves , Suhas Kumar
IPC: H04L9/06 , G06F17/16 , H04L29/06 , H04L12/743 , G11C11/16
Abstract: An input string is mapped to a vector of input voltages. The vector is applied to input rows of a dot product engine having memristor elements at intersections of the input rows and output columns. A hash of the input string is determined based on output of the dot product engine as to which the vector of input voltages have been applied to the input rows thereof. An output column may be selected from output voltages of the columns, and the hash determined from the selected column. The output voltage of a column is equal to a sum of a product of the input voltage in each input row and a value of the memristor element at the intersection of the input row and the column. The hash can be used within a filtering technique applied to the input string, such as in the context of network security.
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Patent Agency Ranking
6.发明授权公开(公告)号：US11599771B2
公开(公告)日：2023-03-07
申请号：US16260898
申请日：2019-01-29
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Suhas Kumar , Thomas Van Vaerenbergh , John Paul Strachan
Abstract: Recurrent neural networks, and methods therefor, are provided with diagonal and programming fluctuation to find energy global minima. The method may include storing the matrix of weights in memory cells of a crossbar array of a recursive neural network prior to operation of the recursive neural network; altering the weights according to a probability distribution; setting the weights to non-zero values in at least one of the memory cells in a diagonal of the memory cells in the crossbar array; and operating the recursive neural network.
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公开(公告)号：US10380386B1
公开(公告)日：2019-08-13
申请号：US15966600
申请日：2018-04-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： John Paul Strachan , Catherine Graves , Suhas Kumar
Abstract: A crossbar array includes a number of memory elements. A vector input register has N voltage inputs to the crossbar array. A vector output register has M voltage outputs from the crossbar array. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A clustering processor is electronically coupled to the ADC and to the DAC. The clustering processor is configured to program columns of the crossbar array with a set of k cluster center values; apply voltages to rows of the crossbar array where the applied voltages represent a set of data values; and determine a minimum distance of each data value to each k cluster center values based on the voltage output from the output register of each of the plurality of the programmed columns.
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公开(公告)号：US20180114899A1
公开(公告)日：2018-04-26
申请号：US15331652
申请日：2016-10-21
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Suhas Kumar , Kate Norris
CPC classification number: H01L47/00
Abstract: Examples herein relate to negative differential resistance devices. An example negative differential resistance device includes a first electrode and a first negative differential resistance device coupled to the first electrode. A second negative differential device is be coupled to the first negative differential resistance device. The second NDR device is different from the first NDR device. A second electrode is coupled to the second NDR device, and is electrically coupled with the first NDR device and the first electrode.
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公开(公告)号：US11532356B2
公开(公告)日：2022-12-20
申请号：US17223435
申请日：2021-04-06
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Amit S. Sharma , John Paul Strachan , Catherine Graves , Suhas Kumar , Craig Warner , Martin Foltin
Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.
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10.发明申请公开(公告)号：US20200242447A1
公开(公告)日：2020-07-30
申请号：US16260898
申请日：2019-01-29
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Suhas Kumar , Thomas Van Vaerenbergh , John Paul Strachan
Abstract: Recurrent neural networks, and methods therefor, are provided with diagonal and programming fluctuation to find energy global minima. The method may include storing the matrix of weights in memory cells of a crossbar array of a recursive neural network prior to operation of the recursive neural network; altering the weights according to a probability distribution; setting the weights to non-zero values in at least one of the memory cells in a diagonal of the memory cells in the crossbar array; and operating the recursive neural network.
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